DataSheet.jp

74HC08 の電気的特性と機能

74HC08のメーカーはON Semiconductorです、この部品の機能は「Quad 2-Input AND Gate」です。


製品の詳細 ( Datasheet PDF )

部品番号 74HC08
部品説明 Quad 2-Input AND Gate
メーカ ON Semiconductor
ロゴ ON Semiconductor ロゴ 




このページの下部にプレビューと74HC08ダウンロード(pdfファイル)リンクがあります。

Total 7 pages

No Preview Available !

74HC08 Datasheet, 74HC08 PDF,ピン配置, 機能
74HC08
Quad 2−Input AND Gate
HighPerformance SiliconGate CMOS
The 74HC08 is identical in pinout to the LS08. The device inputs are
compatible with Standard CMOS outputs; with pullup resistors, they
are compatible with LSTTL outputs.
Features
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance With the JEDEC Standard No. 7A Requirements
ESD Performance: HBM > 2000 V; Machine Model > 200 V
Chip Complexity: 24 FETs or 6 Equivalent Gates
These are PbFree Devices
1
A1
B1 2
4
A2
B2 5
9
A3
B3 10
12
A4
B4 13
LOGIC DIAGRAM
PIN 14 = VCC
PIN 7 = GND
3 Y1
6 Y2
Y = AB
8 Y3
11 Y4
Pinout: 14Lead Packages (Top View)
VCC B4 A4 Y4 B3 A3 Y3
14 13 12 11 10 9 8
14
1
http://onsemi.com
MARKING
DIAGRAMS
14
SOIC14
D SUFFIX
CASE 751A
1
HC08G
AWLYWW
14
1
TSSOP14
DT SUFFIX
CASE 948G
14
HC
08
ALYW G
G
1
HC08 = Device Code
A = Assembly Location
WL or L = Wafer Lot
Y = Year
WW or W = Work Week
G or G = PbFree Package
(Note: Microdot may be in either location)
FUNCTION TABLE
Inputs
Output
AB
Y
LL
LH
HL
HH
L
L
L
H
1234567
A1 B1 Y1 A2 B2 Y2 GND
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2007
March, 2007 Rev. 1
1
Publication Order Number:
74HC08/D

1 Page





74HC08 pdf, ピン配列
74HC08
DC CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Parameter
Condition
VCC Guaranteed Limit
(V) 55 to 25°C 85°C 125°C Unit
VIH Minimum HighLevel Input Voltage Vout = 0.1V or VCC 0.1V
|Iout| 20mA
2.0
1.50
1.50 1.50
V
3.0 2.10 2.10 2.10
4.5 3.15 3.15 3.15
6.0 4.20 4.20 4.20
VIL Maximum LowLevel Input Voltage Vout = 0.1V or VCC 0.1V
|Iout| 20mA
2.0
0.50
0.50 0.50
V
3.0 0.90 0.90 0.90
4.5 1.35 1.35 1.35
6.0 1.80 1.80 1.80
VOH Minimum HighLevel Output Voltage Vin = VIH or VIL
|Iout| 20mA
2.0 1.9
4.5 4.4
6.0 5.9
1.9 1.9 V
4.4 4.4
5.9 5.9
Vin =VIH or VIL
|Iout| 2.4mA
|Iout| 4.0mA
|Iout| 5.2mA
3.0
4.5
6.0
VOL Maximum LowLevel Output Voltage Vin = VIH or VIL
|Iout| 20mA
2.0
4.5
6.0
2.48
3.98
5.48
0.1
0.1
0.1
2.34 2.20
3.84 3.70
5.34 5.20
0.1 0.1
0.1 0.1
0.1 0.1
V
Vin = VIH or VIL
|Iout| 2.4mA
|Iout| 4.0mA
|Iout| 5.2mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33 0.40
0.33 0.40
0.33 0.40
Iin
Maximum Input Leakage Current
Vin = VCC or GND
6.0 ±0.1 ±1.0 ±1.0 mA
ICC Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0mA
6.0 2.0
20 40 mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book (DL129/D).
AC CHARACTERISTICS (CL = 50pF, Input tr = tf = 6ns)
Symbol
Parameter
VCC Guaranteed Limit
(V) 55 to 25°C 85°C 125°C Unit
tPLH,
tPHL
Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 2)
2.0 75
3.0 30
4.5 15
6.0 13
95 110 ns
40 55
19 22
16 19
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
2.0 75
3.0 27
4.5 15
6.0 13
95 110 ns
32 36
19 22
16 19
Cin Maximum Input Capacitance
10 10 10 pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor HighSpeed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V, VEE = 0 V
CPD Power Dissipation Capacitance (Per Buffer)*
20 pF
* Used to determine the noload dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
ON Semiconductor HighSpeed CMOS Data Book (DL129/D).
http://onsemi.com
3


3Pages


74HC08 電子部品, 半導体
74HC08
PACKAGE DIMENSIONS
TSSOP14
CASE 948G01
ISSUE B
0.15 (0.006) T U S
2X L/2 14
L
PIN 1
IDENT.
1
14X K REF
0.10 (0.004) M T U S V S
N
8
B
UN
0.25 (0.010)
M
F
7 DETAIL E
0.15 (0.006) T U S
A
V
ÇÇÇÉÉÇÇÇÉÉÇÇÇÉÉJ J1
K
K1
SECTION NN
0.10 (0.004)
TSEATING
PLANE
D
C
G
H DETAIL E
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE W.
W
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 4.90 5.10 0.193 0.200
B 4.30 4.50 0.169 0.177
C −−− 1.20 −−− 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
G 0.65 BSC
0.026 BSC
H 0.50 0.60 0.020 0.024
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L 6.40 BSC
0.252 BSC
M 0_ 8_ 0_ 8_
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
6

6 Page



ページ 合計 : 7 ページ
 
PDF
ダウンロード
[ 74HC08 データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
74HC00

Quad 2-input NAND gate

Philips
Philips
74HC00

QUADRUPLE 2-INPUT NAND GATES

Diodes
Diodes
74HC00

Quad 2-input NAND gate

NXP Semiconductors
NXP Semiconductors
74HC01

Quad. 2-input NAND Gates (with open drain outputs)

Hitachi
Hitachi


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap