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5P49V5943 の電気的特性と機能

5P49V5943のメーカーはIntegrated Device Technologyです、この部品の機能は「Programmable Clock Generator」です。


製品の詳細 ( Datasheet PDF )

部品番号 5P49V5943
部品説明 Programmable Clock Generator
メーカ Integrated Device Technology
ロゴ Integrated Device Technology ロゴ 




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5P49V5943 Datasheet, 5P49V5943 PDF,ピン配置, 機能
Programmable Clock Generator
5P49V5943
DATASHEET
Description
The 5P49V5943 is a programmable clock generator intended
for high performance consumer, networking, industrial,
computing, and data-communications applications.
Configurations may be stored in on-chip One-Time
Programmable (OTP) memory or changed using I2C
interface. This is IDTs fifth generation of programmable clock
technology (VersaClock® 5).
The frequencies are generated from a single input reference
clock.
Two select pins allow up to 4 different configurations to be
programmed and accessible using processor GPIOs or
bootstrapping. The different selections may be used for
different operating modes (full function, partial function, partial
power-down), regional standards (US, Japan, Europe) or
system production margin testing.
The device may be configured to use one of two I2C
addresses to allow multiple devices to be used in a system.
Pin Assignment
CLKIN
CLKINB
VDDA
VDD
SD/OE
20 19 18 17 16
1 15
2 14
3
EPAD
13
4 12
5 11
6 7 8 9 10
VDDO1
OUT1
OUT1B
GND
GND
20-pin VFQFPN
Features
Generates up to two independent output frequencies
High performance, low phase noise PLL, <0.7 ps RMS
typical phase jitter on outputs:
– PCIe Gen1, 2, 3 compliant clock capability
– USB 3.0 compliant clock capability
– 1 GbE and 10 GbE
Two fractional output dividers (FODs)
Independent Spread Spectrum capability on each output
pair
Four banks of internal non-volatile in-system
programmable or factory programmable OTP memory
I2C serial programming interface
One reference LVCMOS output clock
Two universal output pairs:
– Each configurable as one differential output pair or two
LVCMOS outputs
I/O Standards:
– Single-ended I/Os: 1.8V to 3.3V LVCMOS
– Differential I/Os - LVPECL, LVDS and HCSL
Input frequency ranges:
– LVDS, LVPECL, HCSL Differential Clock Input (CLKIN,
CLKINB) – 1MHz to 350MHz
Output frequency ranges:
– LVCMOS Clock Outputs – 1MHz to 200MHz
– LVDS, LVPECL, HCSL Differential Clock Outputs –
1MHz to 350MHz
Individually selectable output voltage (1.8V, 2.5V, 3.3V) for
each output pair
Programmable loop bandwidth
Programmable output to output skew
Programmable slew rate control
Individual output enable/disable
Power-down mode
1.8V, 2.5V or 3.3V core VDDD, VDDA
Available in 20-pin VFQFPN 3mm x 3mm package
-40° to +85°C industrial temperature operation
5P49V5943 NOVEMBER 11, 2016
1 ©2015 Integrated Device Technology, Inc.

1 Page





5P49V5943 pdf, ピン配列
5P49V5943 DATASHEET
Table 1: Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
ePAD
Name
CLKIN
CLKINB
VDDA
VDD
Type
Input
Pull-down
Input
Pull-down
Power
Power
SD/OE
Input
Pull-down
SEL1/SDA
SEL0/SCL
VDDO2
OUT2
OUT2B
GND
GND
OUT1B
OUT1
VDDO1
GND
VDDD
GND
VDDO0
Input
Input
Power
Output
Output
Power
Power
Output
Output
Power
Power
Power
Power
Power
Pull-down
Pull-down
OUT0_SELB_I2C Input/Output Pull-down
Power
Description
Differential clock input. Weak 100kohms internal pull-down.
Complementary differential clock input. Weak 100kohms internal pull-down.
Analog functions power supply pin. Connect to 1.8V to 3.3V. VDDA and VDDD
should have the same voltage applied.
Power supply pin. Connect to 1.8 to 3.3V.
Enables/disables the outputs (OE) or powers down the chip (SD). The SH bit
controls the configuration of the SD/OE pin. The SH bit needs to be high for
SD/OE pin to be configured as SD. The SP bit (0x02) controls the polarity of the
signal to be either active HIGH or LOW only when pin is configured as OE
(Default is active LOW.) Weak internal pull down resistor. When configured as
SD, device is shut down, differential outputs are driven high/low, and the single-
ended LVCMOS outputs are driven low. When configured as OE, and outputs are
disabled, the outputs can be selected to be tri-stated or driven high/low,
depending on the programming bits as shown in the SD/OE Pin Function Truth
table.
Configuration select pin, or I2C SDA input as selected by OUT0_SEL_I2CB.
Weak internal pull down resistor.
Configuration select pin, or I2C SCL input as selected by OUT0_SEL_I2CB.
Weak internal pull down resistor.
Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for
OUT2/OUT2B.
Output Clock 2. Please refer to the Output Drivers section for more details.
Complementary Output Clock 2. Please refer to the Output Drivers section for
more details.
Connect to ground.
Connect to ground.
Complementary Output Clock 1. Please refer to the Output Drivers section for
more details.
Output Clock 1. Please refer to the Output Drivers section for more details.
Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for
OUT1/OUT1B.
Connect to ground.
Digital functions power supply pin. Connect to 1.8 to 3.3V. VDDA and VDDB
should have the same voltage applied.
Connect to ground.
Power supply pin for OUT0_SEL_I2CB. Connect to 1.8 to 3.3V. Sets output
voltage levels for OUT0.
Latched input/LVCMOS Output. At power up, the voltage at the pin
OUT0_SEL_I2CB is latched by the part and used to select the state of pins 8
and 9. If a weak pull up (10Kohms) is placed on OUT0_SEL_I2CB, pins 8 and 9
will be configured as hardware select pins, SEL1 and SEL0. If a weak pull down
(10Kohms) is placed on OUT0_SEL_I2CB or it is left floating, pins 8 and 9 will
act as the SDA and SCL pins of an I2C interface. After power up, the pin acts as
a LVCMOS reference output.
Connect to ground pad.
NOVEMBER 11, 2016
3 PROGRAMMABLE CLOCK GENERATOR


3Pages


5P49V5943 電子部品, 半導体
5P49V5943 DATASHEET
Output Skew
For outputs that share a common output divide value, there
will be the ability to skew outputs by quadrature values to
minimize interaction on the PCB. The skew on each output
can be adjusted from 0 to 360 degrees. Skew is adjusted in
units equal to 1/32 of the VCO period. So, for 100 MHz output
and a 2800 MHz VCO, you can select how many 11.161pS
units you want added to your skew (resulting in units of 0.402
degrees). For example, 0, 0.402, 0.804, 1.206, 1.408, and so
on. The granularity of the skew adjustment is always
dependent on the VCO period and the output period.
Output Drivers
The OUT1 to OUT2 clock outputs are provided with
register-controlled output drivers. By selecting the output drive
type in the appropriate register, any of these outputs can
support LVCMOS, LVPECL, HCSL or LVDS logic levels
The operating voltage ranges of each output is determined by
its independent output power pin (VDDO) and thus each can
have different output voltage levels. Output voltage levels of
2.5V or 3.3V are supported for differential HCSL, LVPECL
operation, and 1. 8V, 2.5V, or 3.3V are supported for LVCMOS
and differential LVDS operation.
Each output may be enabled or disabled by register bits.
When disabled an output will be in a logic 0 state as
determined by the programming bit table shown on page 6.
LVCMOS Operation
When a given output is configured to provide LVCMOS levels,
then both the OUTx and OUTxB outputs will toggle at the
selected output frequency. All the previously described
configuration and control apply equally to both outputs.
Frequency, phase alignment, voltage levels and enable /
disable status apply to both the OUTx and OUTxB pins. The
OUTx and OUTxB outputs can be selected to be
phase-aligned with each other or inverted relative to one
another by register programming bits. Selection of
phase-alignment may have negative effects on the phase
noise performance of any part of the device due to increased
simultaneous switching noise within the device.
Device Hardware Configuration
The 5P49V5943 supports an internal One-Time
Programmable (OTP) memory that can be pre-programmed
at the factory with up to 4 complete device configuration.
These configurations can be over-written using the serial
interface once reset is complete. Any configuration written via
the programming interface needs to be re-written after any
power cycle or reset. Please contact IDT if a specific
factory-programmed configuration is desired.
Device Start-up & Reset Behavior
The 5P49V5943 has an internal power-up reset (POR) circuit.
The POR circuit will remain active for a maximum of 10ms
after device power-up.
Upon internal POR circuit expiring, the device will exit reset
and begin self-configuration.
The device will load internal registers according to Table 3.
Once the full configuration has been loaded, the device will
respond to accesses on the serial port and will attempt to lock
the PLL to the selected source and begin operation.
Power Up Ramp Sequence
VDDA and VDDD must ramp up together. VDDO0~2 must
ramp up before, or concurrently with, VDDA and VDDD. All
power supply pins must be connected to a power rail even if
the output is unused. All power supplies must ramp in a linear
fashion and ramp monotonically.
VDDO0~2
VDDA
VDDD
PROGRAMMABLE CLOCK GENERATOR
6
NOVEMBER 11, 2016

6 Page



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部品番号部品説明メーカ
5P49V5943

Programmable Clock Generator

Integrated Device Technology
Integrated Device Technology
5P49V5944

Programmable Clock Generator

Integrated Device Technology
Integrated Device Technology


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