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PDF ISLA222S Data sheet ( Hoja de datos )
| Número de pieza | ISLA222S | |
| Descripción | High Speed Serial Output ADC | |
| Fabricantes | Intersil | |
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DATASHEET
Dual 12-bit, 250/200/125 MSPS JESD204B High Speed
Serial Output ADC
ISLA222S
The ISLA222S is a series of low-power, high-performance,
dual-channel 12-bit, analog-to-digital converters. Designed
with FemtoCharge™ technology on a standard CMOS process,
the series supports sampling rates of up to 250MSPS. The
ISLA222S is part of a pin-compatible family of 12- and 14-bit
dual-channel A/Ds with maximum sample rates ranging from
125MSPS to 250MSPS and shares the same analog core as
Intersil's proven ISLA222P series of ADCs. The family
minimizes power consumption while providing state of the art
dynamic performance, offering an optimal performance vs
power trade-off.
Differentiating the ISLA222S from the ISLA222P is its highly
configurable, JESD204B-compliant, high-speed serial output
link. The link offers data rates up to 4.375Gbps per lane and
multiple packing modes. It can be configured to use one, two,
or three lanes to transmit the conversion data, allowing for
flexibility in the receiver design. The SERDES transmitter also
provides deterministic latency and multi-chip time alignment
support to satisfy an application's complex synchronization
requirements.
A Serial Peripheral Interface (SPI) port allows for extensive
configurability of the JESD204B transmitter including access
to its built-in link and transport layer test patterns. The SPI port
also provides control for numerous additional features
including the fine gain and offset adjustments of the two ADC
cores as well as the programmable clock divider, enabling 2x
and 4x harmonic clocking.
The ISLA222S is available in a space saving 7mmx7mm 48 Ld
QFN package. The package features a thermal pad for
improved thermal performance and is specified over the full
industrial temperature range (-40°C to +85°C).
Features
• JESD204A/B high-speed data interface
- JESD204A compliant
- JESD204B device subclass 0 compliant
- JESD204B device subclass 2 compatible
- Up to 3 JESD204 output lanes running up to 4.375Gbps
- Highly configurable JESD204 transmitter
• Multiple chip time alignment and deterministic latency
support (JESD204B device subclass 2)
• SPI programmable debugging features and test patterns
• 48-pin QFN 7mmx7mm package
Key Specifications
• SNR at 250/200/125MSPS
70.6/71.2/71.7 dBFS fIN = 30MHz
70.3/70.7/70.9 dBFS fIN = 190MHz
• SFDR at 250/200/125MSPS
87/93/95 dBc fIN = 30MHz
84/93/86 dBc fIN = 190MHz
• Total Power Consumption: 989mW at 250MSPS
Applications
• Radar and satellite antenna array processing
• Broadband communications and microwave receivers
• High-performance data acquisition
• Communications test equipment
• High-speed medical imaging
Pin-compatible Family
MODEL
ISLA224S25
ISLA224S20
ISLA224S12
ISLA222S25
ISLA222S20
ISLA222S12
RESOLUTION
14
14
14
12
12
12
SPEED
(MSPS)
250
200
125
250
200
125
FIGURE 1. SERDES DATA EYE AT 4.375Gbps
July 6, 2015
FN8302.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2012, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
ISLA222S
Absolute Maximum Ratings
Thermal Information
AVDD to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V
OVDD to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.4V to 2.1V
AVSS to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
Analog Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Clock Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V
Logic Input to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Logic Inputs to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V
Latch-up (Tested per JESD-78C; Class 2, Level A). . . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
48 Ld QFN (Notes 3, 4, 5) . . . . . . . . . . . . . .
24
0.4
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
4. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
5. For solder stencil layout and reflow guidelines, please see Tech Brief. TB389
Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V,
TA = -40°C to +85°C (typical specifications at +25°C), AIN = -2dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade). Boldface limits apply
across the operating temperature range, -40°C to +85°C.
ISLA222S25
ISLA222S20
ISLA222S12
PARAMETER
SYMBOL
MIN MAX MIN MAX MIN MAX
TEST CONDITIONS (Note 6) TYP (Note 6) (Note 6) TYP (Note 6) (Note 6) TYP (Note 6) UNIT
DC SPECIFICATIONS
Analog Input
Full Scale Analog Input
Range
VFS Differential
1.9 2.00 2.1
1.9 2.0 2.1
1.9 2.0 2.1
VP-P
Input Resistance
Input Capacitance
Full Scale Range Temp.
Drift
RIN
CIN
AVTC
Differential
Differential
Full Temp
600 600 600 Ω
7.4 7.4 7.4 pF
115 58
58 ppm/°C
Input Offset Voltage
Gain Error
Common-mode Output
Voltage
VOS
EG
VCM
±1
1
0.94
±1
1
0.94
±1
1
0.94
mV
%
V
Common Mode Input
Current (per pin)
ICM
6.0 6.0 6.0 µA/MSPS
Clock Inputs
Inputs Common Mode
Voltage
0.9 0.9 0.9 V
CLKP, CLKN Swing
1.8 1.8 1.8 V
Power Requirements
1.8V Analog Supply
Voltage
AVDD
1.8 1.8 1.8 V
1.8V Digital Supply
Voltage
OVDD
1.8 1.8 1.8 V
1.8V Analog Supply
Current
IAVDD
353 397
324 365
282 316
mA
1.8V Digital Supply
Current
IOVDD Minimum number of
lanes active
195 218
179 200
123 173
mA
Submit Document Feedback
5
FN8302.1
July 6, 2015
5 Page 
ISLA222S
Typical Performance Curves All Typical Performance Characteristics apply under the following conditions unless
otherwise noted: AVDD = OVDD = 1.8V, TA = +25°C, AIN = -2dBFS, fIN = 105MHz, fSAMPLE = 250MSPS. (Continued)
90 -75
85
SFDR
80
-80
H3
-85
75
SNR
70
65
-90
-95
-100
H2
60
50
100 150 200
SAMPLE RATE (MSPS)
250
FIGURE 9. SNR AND SFDR vs fSAMPLE
300
-105
70
90 110 130 150 170 190 210 230 250
SAMPLE RATE (MSPS)
FIGURE 10. HD2 AND HD3 vs fSAMPLE
1000
950
3 LANE OPERATION
900
ADC CONFIGURED FOR
850 SINGLE LANE OPERATION
800
FOR SAMPLE RATE
≤ 150 MSPS
750
700
650
600
ADC CONFIGURED FOR
TWO LANE OPERATION
FOR SAMPLE RATE
≥ 160 MSPS
550 EFFICIENT PACKING
500
40 60 80 100 120 140 160 180 200 220 240
SAMPLE RATE (MSPS)
FIGURE 11. POWER vs fSAMPLE
2.0
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
0
500 1000 1500 2000 2500 3000 3500
CODES
FIGURE 13. INTEGRAL NONLINEARITY (250MSPS)
4000
1.00
0.75
0.50
0.25
0
-0.25
-0.50
-0.75
-1.00
0
500 1000 1500 2000 2500 3000 3500
CODES
FIGURE 12. DIFFERENTIAL NONLINEARITY (250MSPS)
4000
85
80 SFDR
75
70
SNR
65
60
0.7 0.8 0.9
1.0 1.1 1.2 1.3 1.4
INPUT COMMON MODE (V)
FIGURE 14. SNR AND SFDR vs VCM (250MSPS)
1.5
Submit Document Feedback 11
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July 6, 2015
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ISLA222S.PDF ] | |
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