PDF ISL6328 Data sheet ( Hoja de datos )

Número de pieza	ISL6328
Descripción	Dual PWM Controller
Fabricantes	Intersil
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Hay una vista previa y un enlace de descarga de ISL6328 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas
No Preview Available ! NOc1No-T8nO8Rta8REc-CIEtNCOoTuOMErMRMTSMEeIcNELhNDonDEricDEwaDwFl SORwuRE.ipnPNptLeoEArrWstCiClED.ceMEonESmteNIG/rtTsNactS Dual PWM Controller For Powering AMD SVI Split-Plane Processors ISL6328 The ISL6328 dual PWM controller delivers high efficiency and tight regulation from two synchronous buck DC/DC converters. The ISL6328 supports power control of AMD processors, which operate from a serial VID interface (SVI). The dual output ISL6328 features a multi-phase controller to support the Core voltage (VDD) and a single phase controller to power the Northbridge (VDDNB). A precision core voltage regulation system is provided by a one-to-four-phase PWM voltage regulator (VR) controller. The integration of two power MOSFET drivers adds flexibility in layout and reduces the number of external components in the multi-phase section. A single phase PWM controller with integrated driver provides a second precision voltage regulation system for the Northbridge portion of the processor. This monolithic, dual controller with an integrated driver solution provides a cost and space saving power management solution. For applications that benefit from load line programming to reduce bulk output capacitors, the ISL6328 features temperature compensated output voltage droop. The multi-phase portion also includes advanced control loop features for optimal transient response to load application and removal. One of these features is highly accurate, fully differential, continuous DCR current sensing for load line programming and channel current balance. Dual edge modulation is another unique feature, allowing for quicker initial response to high di/dt load transients. The ISL6328 supports Power Savings Mode by dropping the number of phases when the PSI_L bit is set. Features • Processor Core Voltage Via Integrated Multi-Phase Power Conversion • Configuration Flexibility - 1 or 2-Phase Operation with Internal Drivers - 3 or 4-Phase Operation with External PWM Drivers • PSI_L Support - Phase Shedding for Improved Efficiency at Light Load - Diode Emulation in PSI mode - Gate Voltage Optimization • Precision Core Voltage Regulation - Differential Remote Voltage Sensing - 0.6% System Accuracy Over-Temperature • Optimal Processor Core Voltage Transient Response - Adaptive Phase Alignment (APA) - Active Pulse Positioning Modulation • Fully Differential, Continuous DCR Current Sensing - Accurate Load Line Programming - Precision Channel Current Balancing - Temperature Compensated • Serial VID interface Handles up to 3.4MHz Clock Rates • Two Level Overcurrent Protection Allows for High Current Throttling (IDD_SPIKE) • Multi-tiered Overvoltage Protection • Selectable Switching Frequency up to 1MHz • Simultaneous Digital Soft-Start of Both Outputs June 7, 2011 FN7621.1 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 \|Copyright Intersil Americas Inc. 2011. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. 1 page Pin Configuration ISL6328 ISL6328 (48 LD QFN) TOP VIEW 48 47 46 45 44 43 42 41 40 39 38 37 COMP_NB 1 36 PWM4 FB_NB 2 35 PWROK VSEN_NB 3 34 VDDPWRGD DRPCTRL 4 33 PHASE1 SVC 5 32 UGATE1 SVD 6 VCC 7 49 GND 31 BOOT1 30 LGATE1 RSVD 8 29 GVOT OFS 9 28 LGATE2 OCP 10 27 BOOT2 TCOMP1 11 TCOMP2 12 26 UGATE2 25 EN 13 14 15 16 17 18 19 20 21 22 23 24 Functional Pin Descriptions PIN NAME COMP_NB FB_NB VSEN_NB DRPCTRL SVC SVD VCC RSVD OFS PIN NUMBER 1 2 3 4 5 6 7 8 9 DESCRIPTION Output of the internal error amplifier for the Northbridge regulator. Inverting input to the internal error amplifier for the Northbridge regulator. Non-inverting input to the Northbridge regulator precision differential remote-sense amplifier. This pin should be connected to the remote Northbridge sense pin of the processor, VDDNB_SENSE. Droop Control for Core and Northbridge. This pin is used to set up one of four user programmable selections via a resistor: Core Droop On and Northbridge Droop On; Core Droop Off and Northbridge Droop On, Core Droop On and Northbridge Droop Off; Core Droop Off and Northbridge Droop Off. If the resistor is tied to ground, the number of active phases in PSI mode is 1. If the resistor is tied to VCC, the number of active phases in PSI mode is 2. Serial VID clock input from the AMD processor. Serial VID data bi-directional signal to and from the master device on AMD processor. VCC is the bias supply for the ICs small-signal circuitry. Connect this pin to a +5V supply and decouple using a quality 0.1µF ceramic capacitor. RESERVED. Connect this pin directly to the VCC pin. The OFS pin provides a means to program a DC current for generating an offset voltage across the resistor between FB and VSEN. The offset current is generated via an external resistor and precision internal voltage references. The polarity of the offset is selected by connecting the resistor to GND or VCC. For no offset, the OFS pin should be left unconnected. 5 FN7621.1 June 7, 2011 5 Page ISL6328 Electrical Specifications Boldface limits apply over the operating temperature range. (Continued) PARAMETER TEST CONDITIONS MIN MAX (Note 6) TYP (Note 6) UNITS POWER GOOD Overvoltage Threshold VSEN Rising VDAC + 220mV VDAC + 325mV V Undervoltage Threshold VSEN Falling VDAC - 345mV VDAC - 190mV mV Power-Good Hysteresis 50 mV OVERVOLTAGE PROTECTION OVP Trip Level OVP Lower Gate Release Threshold VDAC = 1.1V 1.75 0.35 1.79 1.85 V V SWITCHING TIME (Note 7) [See “Timing Diagram” on page 12] UGATE Rise Time LGATE Rise Time UGATE Fall Time LGATE Fall Time UGATE Turn-On Non-overlap LGATE Turn-On Non-overlap GATE DRIVE RESISTANCE tRUGATE; VPVCC = 8V, 3nF Load, 10% to 90% 26 ns tRLGATE; VPVCC = 8V, 3nF Load, 10% to 90% 18 ns tFUGATE; VPVCC = 12V, 3nF Load, 90% to 10% 18 ns tFLGATE; VPVCC = 12V, 3nF Load, 90% to 10% 12 ns tPDHUGATE; VPVCC = 12V, 3nF Load, Adaptive 10 ns tPDHLGATE; VPVCC = 12V, 3nF Load, Adaptive 10 ns Upper Drive Source Resistance Upper Drive Sink Resistance Lower Drive Source Resistance Lower Drive Sink Resistance SVI INTERFACE VPVCC = 12V, 15mA Source Current VPVCC = 12V, 15mA Sink Current VPVCC = 12V, 15mA Source Current VPVCC = 12V, 15mA Sink Current 2.5  2.0  1.6  1.1  SVC, SVD Input HIGH (VIH) FS resistor tied to GND 0.85 V SVC, SVD Input LOW (VIL) FS resistor tied to GND 0.45 V SVC, SVD Input HIGH (VIH) FS resistor tied to VCC 1.05 V SVC, SVD Input LOW (VIL) FS resistor tied to VCC 0.55 V SVD Low Level Output Voltage SVC, SVD Leakage (Note 7) 510 Resistor to 1.8V 0.4 V ±5 µA NOTES: 6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 7. Limits should be considered typical and are not production tested. 11 FN7621.1 June 7, 2011 11 Page

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