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ISL33001 の電気的特性と機能

ISL33001のメーカーはIntersilです、この部品の機能は「I2C Bus Buffer」です。


製品の詳細 ( Datasheet PDF )

部品番号 ISL33001
部品説明 I2C Bus Buffer
メーカ Intersil
ロゴ Intersil ロゴ 




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ISL33001 Datasheet, ISL33001 PDF,ピン配置, 機能
I2C Bus Buffer with Rise Time Accelerators and
Hot Swap Capability
ISL33001, ISL33002, ISL33003
The ISL33001, ISL33002, ISL33003 are 2-Channel Bus Buffers
that provide the buffering necessary to extend the bus
capacitance beyond the 400pF maximum specified by the I2C
specification. In addition, the ISL33001, ISL33002, ISL33003
feature rise time accelerator circuitry to reduce power
consumption from passive bus pull-up resistors and improve
data-rate performance. All devices also include hot swap circuitry
to prevent corruption of the data and clock lines when I2C devices
are plugged into a live backplane, and the ISL33002 and
ISL33003 add level translation for mixed supply voltage
applications. The ISL33001, ISL33002, ISL33003 operate at
supply voltages from +2.3V to +5.5V at a temperature range of
-40°C to +85°C.
Summary of Features
PART
NUMBER
ISL33001
ISL33002
ISL33003
LEVEL
TRANSLATION
No
Yes
Yes
ENABLE
PIN
Yes
No
Yes
READY
PIN
Yes
No
No
ACCELERATOR
DISABLE
No
Yes
No
Related Literature
AN1543, “ISL33001MSOPEVAL1Z, ISL33002MSOPEVAL1Z,
ISL33003MSOPEVAL1Z Evaluation Board User’s Manual”
AN1637, “Level Shifting Between 1.8V and 3.3V Using I2C
Buffers”
Features
• 2 Channel I2C compatible bi-directional buffer
• +2.3VDC to +5.5VDC supply range
• >400kHz operation
• Bus capacitance buffering
• Rise time accelerators
• Hot swapping capability
• ±6kV Class 3 HBM ESD protection on all pins
• ±12kV HBM ESD protection on SDA/SCL pins
• Enable pin (ISL33001 and ISL33003)
• Logic level translation (ISL33002 and ISL33003)
• READY logic pin (ISL33001)
• Accelerator disable pin (ISL33002)
• Pb-free (RoHS Compliant) 8 Ld SOIC (ISL33001 only),
8 Ld TDFN (3mmx3mm) and 8 Ld MSOP packages
• Low quiescent current . . . . . . . . . . . . . . . . . . . . . . . 2.1mA typ
• Low shutdown current . . . . . . . . . . . . . . . . . . . . . . . . 0.5µA typ
Applications
• I2C bus extender and capacitance buffering
• Server racks for telecom, datacom, and computer servers
• Desktop computers
• Hot-swap board insertion and bus isolation
VCC1 +3.3V
+5.0V
VCC2
µC
SDA
SCL
EN
ISL33003
BACK
PLANE
SDA
SCL
GND
I2C
DEVICE
A
I2C
DEVICE
B
100kHz I2C BUS WITH 2.7kΩ PULL-UP RESISTOR
AND 400pF BUS CAPACITANCE
WITHOUT BUFFER
WITH BUFFER
FIGURE 1. TYPICAL OPERATING CIRCUIT
TIME (2µs/DIV)
FIGURE 2. BUS ACCELERATOR PERFORMANCE
July 11, 2014
FN7560.6
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas LLC. 2010-2014. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.

1 Page





ISL33001 pdf, ピン配列
ISL33001, ISL33002, ISL33003
Pin Configurations (Continued)
ISL33003
(8 LD TDFN)
TOP VIEW
ISL33003
(8 LD MSOP)
TOP VIEW
VCC2 1
SCL_OUT 2
SCL_IN 3
GND 4
PAD
8 VCC1
7 SDA_OUT
6 SDA_IN
5 EN
VCC2 1
SCL_OUT 2
SCL_IN 3
GND 4
8 VCC1
7 SDA_OUT
6 SDA_IN
5 EN
Pin Descriptions
PIN
PIN NAME NUMBER
FUNCTION
NOTES
VCC1
8 VCC1 power supply, +2.3V to +5.5V. Decouple VCC1 to ground with a high frequency
0.01µF to 0.1µF capacitor.
VCC2
GND
1 VCC2 power supply, +2.3V to +5.5V. Decouple VCC2 to ground with a high frequency ISL33002 (8 LD TDFN, 8 LD MSOP)
0.01µF to 0.1µF capacitor. In level shifting applications, SDA_OUT and SCL_OUT logic ISL33003 (8 LD TDFN, 8 LD MSOP)
thresholds are referenced to VCC2 supply levels. Connect pull-up resistors on these
pins to VCC2.
4 Device Ground Pin
EN 1 Buffer Enable Pin. Logic “0” disables the device. Logic “1” enables the device. Logic ISL33001 (8 LD TDFN, 8 LD SOIC, MSOP)
5 threshold referenced to VCC1.
ISL33003 (8 LD TDFN, 8 LD MSOP)
READY
ACC
SDA_IN
5 Buffer active ‘Ready’ open drain logic output. When buffer is active, READY is high ISL33001 only
impedance. When buffer is inactive, READY is low impedance to ground. Connect to
10kΩ pull-up resistor to VCC1.
5 Rise Time Accelerator Enable Pin. Logic “0” disables the accelerator. Logic “1”
enables the accelerator. Logic threshold referenced to VCC1.
ISL33002 only
6 Data I/O Pins
SDA_OUT
7
SCL_IN
3 Clock I/O Pins
SCL_OUT
2
PAD Thermal pad should be connected to ground or floated.
Thermal Pad; TDFN only
Submit Document Feedback
3
FN7560.6
July 11, 2014


3Pages


ISL33001 電子部品, 半導体
ISL33001, ISL33002, ISL33003
Test Circuits and Waveforms
- SDA_OUT and SCL pins connected to VCC
- Enable Delay Time Measured on ISL33001 only
- ISL33003 performance inferred from ISL33001
- If tDELAY1 < tEN-LH then tDELAY2 = tEN-LH + tIDLE + tREADY-LH
- If tDELAY1 > tEN-LH then tDELAY2 = tEN-LH + tREADY-LH
VCC
VEN
0.5*VCC
0V
VCC
0.5*VCC
VSDA_IN
VREADY
0.5*VCC
0V
tDELAY1
tREADY-LH
tDELAY2
FIGURE 3. ENABLE DELAY TIME
- VSDA_IN = VSDA_OUT = VSCL_OUT = VEN = VCC
- EN Logic Input must be high for t > Enable Delay (tEN_LH)
prior to SCL_IN transition
- Bus Idle Time Measured on ISL33001 only
- ISL33002 and ISL33003 performance inferred from ISL33001
VCC
VSCL_IN
0V
VCC
VREADY
0V
0.5VCC
0.5VCC
tIDLE
FIGURE 4. BUS IDLE TIME
+3.3V
10kΩ
SCL_OUT
10kΩ
SCL_IN
VIN
0.2V
VCC1
10kΩ
SDA_OUT
GND
SDA_IN
VIN
0.2V
10kΩ
0.2V
SCL_IN OR
SDA_IN
SCL_OUT OR
SDA_OUT
VO
VOS = VO - 0.2V
FIGURE 5A. TEST CIRCUIT
FIGURE 5B. MEASUREMENT POINTS
FIGURE 5. INPUT TO OUTPUT OFFSET VOLTAGE
+2.7V
900Ω
SCL_OUT
900Ω
SCL_IN
0V
VCC1
900Ω
SDA_OUT
GND
SDA_IN
0V
900Ω
SCL_OUT
VOL
SDA_OUT
VOL
VCC1
VCC1
FIGURE 6A. TEST CIRCUIT
FIGURE 6B. MEASUREMENT POINTS
FIGURE 6. OUTPUT LOW VOLTAGE
Submit Document Feedback
6
FN7560.6
July 11, 2014

6 Page



ページ 合計 : 18 ページ
 
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共有リンク

Link :


部品番号部品説明メーカ
ISL33001

I2C Bus Buffer

Intersil
Intersil
ISL33002

I2C Bus Buffer

Intersil
Intersil
ISL33003

I2C Bus Buffer

Intersil
Intersil


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