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PDF LV8498CT Data sheet ( Hoja de datos )
| Número de pieza | LV8498CT | |
| Descripción | Constant-current Driver IC | |
| Fabricantes | ON Semiconductor | |
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Ordering number : ENA1625B
LV8498CT
Bi-CMOS IC
For VCMs
Constant-current Driver IC
http://onsemi.com
Overview
The LV8498CT is a constant current driver IC for voice coil motors that supports I2C control integrating a
digital/analog converter (DAC). It uses an ultraminiature WLP package and includes a current detection resistor for
constant current control, which makes the IC ideal for miniaturization of camera modules intended for use in
camera-equipped mobile phones. The output transistor has a low on-resistance of 1Ω and the resistance of the built-in
current detection resistor is 1Ω, which minimizes the voltage loss and helps withstand voltage drop in VCC. The
function is incorporated, which, by changing the current in a stepped pattern while taking time at rise and fall of the
output current, provides the current a slope, improving the converging stability of the voice coil motor (current slope
function).
Functions
• Constant current driver for voice coil motors.
• I2C bus control supported.
• Constant current control enabled by DAC (10 bits).
• Wide operating voltage range (2.2 to 5.0V).
• Built-in current detection resistor.
• 6-pin WLP package used (1.27 × 0.87 × 0.25mm).
• Built-in voltage drop protection circuit (VCC = 2V output off).
• Built-in thermal protection circuit.
• Low output block total-resistance of 2Ω helps withstand voltage drop in VCC. (Current detection resistance + output
transistor on-resistance).
• Built-in VCM overshoot preventive function (current slope function).
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Symbol
Conditions
Maximum supply voltage
Output voltage
Input voltage
GND pin source current
Allowable power dissipation
VCC max
VOUT max
VIN max
IGND
Pd max
SCL, SDA, ENA
With specified substrate *
Operating temperature
Topr
Storage temperature
Tstg
* Specified substrate : 40mm × 40mm × 1.6mm, Single layer glass epoxy substrate
Ratings
5.5
VCC + 0.5
5.5
200
350
-30 to +85
-40 to +150
Unit
V
V
V
mA
mW
°C
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Semiconductor Components Industries, LLC, 2013
June, 2013
53011 SY/52511 SY/31710 SY 20091119-S00001 No.A1625-1/8
1 page  
LV8498CT
I2C bus transmission method
Start and stop conditions
The I2C bus requires that the state of SDA be preserved while SCL is high as shown in the timing diagram below during a
data transfer operation.
SCL
SDA
ts2
th2
When data is not being transferred, both SCL and SDA are in the high state. The start condition is generated and access is
started when SDA is changed from high to low while SCL and SDA are high.
Conversely, the stop condition is generated and access is ended when SDA is changed from low to high while SCL is
high.
Start condition
Stop condition
SCL
SDA
th1
th3
Data transfer and acknowledgement response
After the start condition has been generated, the data is transferred one byte (8 bits) at a time. Generally, in an I2C bus, a
unique 7-bit slave address is assigned to each device, and the first byte of the transfer data is allocated to the 7-bit slave
address and to the command (R/W) indicating the transfer direction of the subsequent data. However, this IC is provided
with only a write mode for receiving the data. Every time 8 bits of data for each byte are transferred, the ACK signal is
sent from the receiving end to the sending end. Immediately after the clock pulse of SCL bit 8 in the data transferred has
fallen to low, SDA at the sending end is released, and SDA is set to low at the receiving end, causing the ACK signal to be
sent. When, after the receiving end has sent the ACK signal, the transfer of the next byte remains in the receiving status,
the receiving end releases SDA at the falling edge of the ninth SCL clock.
Start
M L AM
S Slave address S W C S
B B KB
Data
L AM
SCS
BKB
SCL
SDA
1st byte
A1 A2 A3 A4 A5 A6 A7 0
2nd byte
PD X D9 D8 D7 D6 D5 D4
LA M
SC S
BK B
Data
L AM
SCS
BKB
Data
LA
SC
BK
Stop
SCL
SDA
3rd byte
D3 D2 D1 D0 X X X X
4th byte
ST2 ST1 ST0TM2TM1TM0 X X
T CARE
No.A1625-5/8
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet LV8498CT.PDF ] | |
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