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PDF LC72722PMS Data sheet ( Hoja de datos )
| Número de pieza | LC72722PMS | |
| Descripción | Single-Chip RDS Signal-Processing System IC | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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Ordering number : ENA2156
LC72722PMS
CMOS IC
Single-Chip RDS
Signal-Processing System IC
http://onsemi.com
Overview
The LC72722PMS is a single-chip system IC that implement the signal processing required by the European
Broadcasting Union RDS (Radio Data System) standard and by the US NRSC (National Radio System Committee)
RBDS (Radio Broadcast Data System) standard. This IC include band-pass filter, demodulator, synchronization, and
error correction circuits as well as data buffer RAM on chip and perform effective error correction using a soft-decision
error correction technique.
Functions
• Band-pass filter : switched capacitor filter (SCF)
• Demodulator : RDS data clock regeneration and demodulated data reliability information
• Synchronization : Block synchronization detection
(with variable backward and forward protection conditions)
• Error correction : Soft-decision/hard-decision error correction
• Buffer RAM : Adequate for 24 blocks of data (about 500ms) and flag memory
• Data I/O : CCB interface (power on reset)
Features
• Error correction capability improved by soft-decision error correction
• The load on the control microprocessor can be reduced by storing decoded data in the on-chip data buffer RAM.
• Two synchronization detection circuits provide continuous and stable detection of the synchronization.
• Data can be read out starting with the backward-protection block data after a synchronization reset.
• Fully adjustment free
Specifications
• Operating power-supply voltage :
• Operating temperature :
• Package :
4.5 to 5.5V
-40 to +85°C
MFP24(375mil)
• CCB is ON Semiconductor® ’s original format. All addresses are managed
by ON Semiconductor® for this format.
• CCB is a registered trademark of Semiconductor Components Industries, LLC.
Semiconductor Components Industries, LLC, 2013
June, 2013
N1412HK B8-4452 No. A2156-1/18
1 page  
LC72722PMS
Block Diagram
+5.0V
Vdda
Vssa
MPXIN
VREF
FLOUT
CIN
REFERENCE
VOLTAGE
ANTIALIASING
FILTER
57kHz
BPF
(SCF)
-
+
VREF
SMOOTHING
FILTER
PLL
(57kHz)
CLOCK
RECOVERY
(1187.5Hz)
DATA
DECODER
DO
CL
DI
CE
T1
T2
T3 to T7
CCB
TEST
RAM
(24 BLOCK DATA)
MEMORY
CONTROL
ERROR
CORRECTION
(SOFT DECISION)
SYNC/EC
CONTROLLER
CLK (4.332MHz)
OSC/DIVIDER
SYNC
SYNC
DETECT-1 DETECT-2
XIN XOUT
+5.0V
Vddd
Vssd
RDS-ID
SYNC
SYR
No. A2156-5/18
5 Page 
LC72722PMS
(7) Crystal oscillator frequency selection (1bit) : XS
XS = 0 : 4.332MHz (Initial value : XS = 0)
XS = 1 : 8.664MHz
(8) Demodulation circuit phase control (2bits) : PL0, PL1
PL0 PL1
Demodulation circuit phase control
0 0/1 < Normal operation > when ARI presence or absence is unclear.
0 If the circuit determines that the ARI signal is absent : 90° phase
1 1 If the circuit determines that the ARI signal is present : 0° phase
Initial values : PL0 = 0, PL1 = 1
Caution : 1. When PL0 is 0 (normal operation), the IC detects the presence or absence of the ARI signal and reproduces
the RDS data by automatically controlling the demodulation phase with respect to the reproduced carrier.
However, the initial phase following a synchronization reset is set by PL1.
2. If PL0 is set to 1, the demodulation circuit phase is locked according to the PL1 setting at either 90° (PL1 = 0) or
0° (PL1 = 1), allowing RDS data to be reproduced. When ARI is not present, PL1 should be set to 0, since the
RDS data is reproduced by detecting at a phase of 90° with respect to the reproduced carrier. When ARI is present,
PL1 should be set to 1, since detection is at 0°. In cases where the ARI presence is known in advance, more stable
reproduction can be achieved by fixing the demodulation phase in this manner.
(9) RDS/RBDS(MMBS) selection (1bit) : RM
RM RBDS
Decoding method
0 None Only RDS data is decoded correctly (Offset word E is not detected.)
1 Provided RDS and MMBS data is decoded correctly (Offset word E is also detected.)
Initial value : RM=0
(10) Output pin settings (3bits) : PT0 to PT2
These bits control the T3, T4, T5, T6, T7, SYNC, and RDS-ID pins
P P P T3 T4 T5
T6
T7
MODE T T T RDCL RDDA RSFT ERROR 57K TP BE1 CORREC ARI-ID TA BE0
012
0 000 −
−
1 1 0 0 − −
2 010
3 110
4 001 −
−
5 1 0 1 −
6 011
7 111
−
−
−
−−
−
−−
−
−
−
−
−
− −
− −−
−
−
−
−
−
−
−
−
−
−
− −−
− −
−−
− −−
− −
− −
−−
− −−
− : open, , : Output enabled ( = reverse polarity)
Initial value : PT0 = 1, PT1 = 1, PT2 = 0 (Mode 3)
Caution : 1. When PT2 is set to 1, the polarity of the T6(ERROR/57K/TP), T7(CORREC/ARI-ID/TA), SYNC,
and RDS-ID pins changes to active high.
2. The output pins (T3 to T7, SYNC, and RDS-ID) are all open-drain pins, and require external pull-up resistors
to output data.
Mode1 (PT2 = 0)
TP = 0 detected
TP = 1 detected
TP = Traffic program code
High (1)
Low (0)
Pin T6 (TP)
No. A2156-11/18
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet LC72722PMS.PDF ] | |
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