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PDF ST7525 Data sheet ( Hoja de datos )
| Número de pieza | ST7525 | |
| Descripción | 192 x 65 Dot Matrix LCD Controller/Driver | |
| Fabricantes | Sitronix | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ST7525 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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Sitronix
ST7525
192 x 65 Dot Matrix LCD Controller/Driver
1. INTRODUCTION
ST7525 is a driver & controller LSI for graphic dot-matrix liquid crystal display systems. It contains 192-segment and
64-common with 1-icon-common driver circuits. This chip is connected directly to a microprocessor which accepts parallel
interface (8-bit), serial peripheral interface (4-line SPI), I2C interface. Display data stores in an on-chip display data RAM
(DDRAM) of 192 x 65 bits. It performs Display Data RAM read/write operation with no external operating clock to minimize
power consumption. In addition, because it contains power supply circuits to drive liquid crystal, it is possible to make a
display system with the fewest components.
2. FEATURES
Single-chip LCD Controller & Driver
Driver Output Circuits
192-segment / 64-common+1-icon-common
On-chip Display Data RAM (DDRAM)
Capacity: 192x65= 12,480 bits
Microprocessor Interface
8-bit parallel bi-directional interface supports
6800-series or 8080-series MPU
4-line SPI
I2C Interface
Built-in Oscillation Circuit
Oscillator requires no external component
Programmable frame frequency
External RST (hardware reset) Pin
Various Display Functions
Partial display
Low Power Consumption Analog Circuit
Voltage booster with internal capacitor (X6)
Wide voltage regulator output range (4.78V~11.5V)
Built-in temperature compensation circuit
Voltage Gradient: -0.05%/°C
Built-in voltage follower for LCD bias voltages:
1/6 ~ 1/9 Bias
Wide Supply Voltage Range
Digital Power (VDD1): 1.8V~3.3V (typical)
Analog Power (VDD2,VDD3): 2.7V~3.3V (typical)
Temperature Range: -30°C ~ +80°C
Package: COG
ST7525
ST7525i
6800 , 8080 , 4-Line Interface
(without I2C Interface)
I2C Interface
Ver 0.3
1/52 2012/08/03
Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice.
1 page  
ST7525 Preliminary
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PAD NAME
SEG64
SEG65
SEG66
SEG67
SEG68
SEG69
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SEG71
SEG72
SEG73
SEG74
SEG75
SEG76
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SEG105
SEG106
SEG107
X
787.5
762.5
737.5
712.5
687.5
662.5
637.5
612.5
587.5
562.5
537.5
512.5
487.5
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87.5
62.5
37.5
12.5
-12.5
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-287.5
Y
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PAD NAME
SEG108
SEG109
SEG110
SEG111
SEG112
SEG113
SEG114
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SEG116
SEG117
SEG118
SEG119
SEG120
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SEG128
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SEG133
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SEG140
SEG141
SEG142
SEG143
SEG144
SEG145
SEG146
SEG147
SEG148
SEG149
SEG150
SEG151
X
-312.5
-337.5
-362.5
-387.5
-412.5
-437.5
-462.5
-487.5
-512.5
-537.5
-562.5
-587.5
-612.5
-637.5
-662.5
-687.5
-712.5
-737.5
-762.5
-787.5
-812.5
-837.5
-862.5
-887.5
-912.5
-937.5
-962.5
-987.5
-1012.5
-1037.5
-1062.5
-1087.5
-1112.5
-1137.5
-1162.5
-1187.5
-1212.5
-1237.5
-1262.5
-1287.5
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-1337.5
-1362.5
-1387.5
Y
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Ver 0.3
5/52 2012/08/03
5 Page 
ST7525 Preliminary
Test Pin
Pin Name
T[0]
T[14:1]
ID[2:0]
TEST[1]
TEST[2]
TEST[3]
Type
Test
Test
Test
Test
Test
Test
Description
This pin is reserved for test only, recommend connecting to TEST[1].
These pins are reserved for test only, recommend setting to floating.
These pins are reserved for test only, recommend setting to VSS1.
This pin is reserved for test only, recommend connecting to T[0].
This pin is reserved for test only, recommend setting to floating.
This pin is reserved for test only, recommend setting to VDD1.
Recommend ITO Resistance
Pin Name
ITO Resistance
VDD1, VDD2, VSS1, VSS2
VMO, VGO, V0(V0I, V0O, V0S), XV0(XV0I, XV0O, XV0S), VDD3, VSS3, SDA(I2C), SCL(I2C)
< 100Ω
< 100Ω
A0, RWR, ERD, CS[1:0], D[7:0], T[14:0], TEST[2:1]
< 1KΩ
BM[2:0], ID[2:0], TEST[3], OSC, CLS
RST *1
< 5KΩ
3KΩ ~ 10KΩ
Note:
1. The RST pin has the most priority over other control signals. It is important to prevent the ESD pulse or external noise
flow into this pin. By adding a series resistor externally or increase the ITO resistance at this pin, the unexpected reset
condition can be solved. The recommended resistance is around 3K~10K Ohm (the optimized value depends on the
LCD module and application system).
2. If using I2C interface mode, the resistance of SDA signal is recommended to be lower than 100Ω
(if the system pull up resistor is 4.7KΩ).
3. If using 4-Line SPI interface with VDD1 less than 2.4V, the SDA signal resistance should be less than 100Ω.
4. This table defines the actual ITO resistance. The actual ITO resistance should in these ranges, not the calculated ITO
resistance value. The ITO tolerance should be considered.
5. The option setting to be “H” should connect to VDD1.
6. The option setting to be “L” should connect to VSS1.
ITO Layout Notes
1. The Limitations include the bottleneck of ITO layout.
2. Make sure that the ITO resistance of all COM outputs are equal, and so are SEG outputs.
3. To avoid the noise in different power systems affect other power system, please separate them on ITO layout.
4. The V0 and XV0 circuits have output pins, input pins and a sensor input. To avoid the power noise affects the sensor of
the power circuits. The trace should be separated by ITO and should be connected together by FPC. The FPC layout
and the equivalent circuit are shown below:
Ver 0.3
11/52
2012/08/03
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ST7525.PDF ] | |
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