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LE2464C の電気的特性と機能

LE2464CのメーカーはON Semiconductorです、この部品の機能は「64-kb I2C CMOS Serial EEPROM」です。


製品の詳細 ( Datasheet PDF )

部品番号 LE2464C
部品説明 64-kb I2C CMOS Serial EEPROM
メーカ ON Semiconductor
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LE2464C Datasheet, LE2464C PDF,ピン配置, 機能
LE2464C
64 kb I2C CMOS Serial EEPROM
Overview
The LE2464C is two-wire serial interface EEPROM (Electrically
Erasable and Programmable ROM). This device realizes high speed
and a high level reliability by high performance CMOS EEPROM
technology. This device is compatible with I2C memory protocol,
therefore it is best suited for application that requires re-writable
nonvolatile parameter memory.
www.onsemi.com
Function
 Capacity
: 64k bits (8k 8 bits)
Single supply voltage
Operating temperature
Interface
: 1.7 V to 3.6 V
: 40ºC to +85ºC
: Two wire serial interface (I2C Bus*)
WLCSP6, 0.80x1.20
 Operating clock frequency : 400 kHz
Low Power consumption
: Standby
: 2 µA (max.)
: Active (Read) : 0.5 mA (max.)
Automatic page write mode : 32 Bytes
Read mode
: Sequential Read and random read
Slave Address : Slave address in 7 bit format is 050 or 054 depending of polarity of pin B3 (TEST)
Erase/Write cycles : 106 cycles (Page Write)
Data Retention : 20 years
High reliability : Adopts proprietary symmetric memory array configuration (USP6947325)
Hardware write protect feature
Noise filters connected to SCL and SDA pins
Incorporates a feature to prohibit write operations under low voltage conditions.
Package
: WLP6(1.200.80) 0.33mm height
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter
Supply voltage
DC input voltage
Over-shoot voltage
Storage temperature
Symbol
Tstg
Conditions
Ratings
0.5 to +4.6
0.5 to VCC+0.5
1.0 to VCC+1.0
65 to +150
Unit
V
V
V
C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
* This product is licensed from Silicon Storage Technology, Inc. (USA).
ORDERING INFORMATION
See detailed ordering and shipping information on page 16 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
August 2016 - Rev. 3
1
Publication Order Number :
LE2464C/D

1 Page





LE2464C pdf, ピン配列
Fast Mode
Parameter
Slave mode SCL clock frequency
SCL clock low time
SCL clock high time
SDA output delay time
SDA data output hold time
Start condition setup time
Start condition hold time
Data in setup time
Data in hold time
Stop condition setup time
SCL SDA rise time
SCL SDA fall time
Bus release time
Noise suppression time
Write time
Standard Mode
Parameter
Slave mode SCL clock frequency
SCL clock low time
SCL clock high time
SDA output delay time
SDA data output hold time
Start condition setup time
Start condition hold time
Data in setup time
Data in hold time
Stop condition setup time
SCL SDA rise time
SCL SDA fall time
Bus release time
Noise suppression time
Write time
LE2464C
Symbol
fSCLS
tLOW
tHIGH
tAA
tDH
tSU.STA
tHD.STA
tSU.DAT
tHD.DAT
tSU.STO
tR
tF
tBUF
tSP
tWC
min
0
1200
600
100
100
600
600
100
0
600
Ratings
typ
1200
max
400
900
300
300
100
5
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Symbol
fSCLS
tLOW
tHIGH
tAA
tDH
tSU.STA
tHD.STA
tSU.DAT
tHD.DAT
tSU.STO
tR
tF
tBUF
tSP
tWC
min
0
4700
4000
100
100
4700
4000
250
0
4000
Ratings
typ
4700
max
100
3500
1000
300
100
5
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
www.onsemi.com
3


3Pages


LE2464C 電子部品, 半導体
Bus timing
SCL
SDA/IN
SDA/OUT
LE2464C
tF tHIGH
tLOW
tSU.STA
tHD.STA
tHD.DAT
tSU.DAT
tAA tDH
tR
tSP
tSU.STO
tSP
tBUF
Write timing
tWC
SCL
SDA
D0
Write Data
Acknowledge
Stop
condition
Start
condition
Pin Function
SCL (Serial clock)
The SCL signal is used to control serial input data timing. The SCL is used to latch input data synchronously
at the rising edge and read output data synchronously at the falling edge.
SDA (Serial input / output data)
The SDA pin is bidirectional for serial data transfer. It is an open-drain structure that needs to be pulled up by
resistor.
TEST (Slave address)
TEST pin represents S2. TEST pulled high (1.8 V) results in 7-bit device address of 0x54. TEST pulled low
results in 7 bit device address of 0x50.
The TEST must be tied to VCC or GND.
WP (Write protect)
When the WP input is high, write protection is enabled. When WP input is either low or floating, write
protection is disabled. The read operation is always activated irrespective of the WP pin status.
www.onsemi.com
6

6 Page



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部品番号部品説明メーカ
LE2464C

64-kb I2C CMOS Serial EEPROM

ON Semiconductor
ON Semiconductor


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