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A25L020C の電気的特性と機能

A25L020CのメーカーはAMICです、この部品の機能は「2Mbit 3V Serial Flash Memory」です。


製品の詳細 ( Datasheet PDF )

部品番号 A25L020C
部品説明 2Mbit 3V Serial Flash Memory
メーカ AMIC
ロゴ AMIC ロゴ 




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A25L020C Datasheet, A25L020C PDF,ピン配置, 機能
A25L020C Series
2Mbit 3V Serial Flash Memory with 100MHz Uniform 4KB Sectors
Document Title
2Mbit 3V Serial Flash Memory with 100MHz Uniform 4KB Sectors
Revision History
Rev. No.
0.0
1.0
1.1
1.2
1.3
History
Initial issue
First version release
P.6: Add small sector protect function
Change 8-pin USON(2*3mm) package outline dimensions
P.1: Add “AEC-Q100 Grade 3 Certification” in FEATURES
Add automotive grade (-AF):
P.31: Add TA=-40°C~+125°C for –AF grade on Table 9
P.34: Add fC (Clock Frequency for the following instructions) Characteristic
for –AF grade on Table 15
P.37: Add –AF grade Part Numbering Scheme
P.38: Add –AF grade Ordering Information
Issue Date
April 01, 2011
April 18, 2011
November 21, 2012
November 14, 2014
December 1, 2014
Remark
Preliminary
Final
(December, 2014, Version 1.3)
AMIC Technology Corp.

1 Page





A25L020C pdf, ピン配列
Block Diagram
HOLD
W
S
C
DIO
DO
Control Logic
Address register
and Counter
A25L020C Series
High Voltage
Generator
I/O Shift Register
256 Byte
Data Buffer
3FFFFh
Status
Register
Size of the
memory area
00000h
000FFh
256 Byte (Page Size)
X Decoder
Pin Descriptions
Pin No.
C
DIO
DO
S
W
HOLD
VCC
VSS
Description
Serial Clock
Serial Data Input 1
Serial Data Output 2
Chip Select
Write Protect
Hold
Supply Voltage
Ground
Notes:
1. The DIO is also used as an output pin when the Fast
Read Dual Output instruction and the Fast Read Dual
Input-Output instruction are executed.
2. The DO is also used as an input pin when the Fast
Read Dual Input-Output instruction is executed.
(December, 2014, Version 1.3)
2
Logic Symbol
VCC
DIO
C
S
W
HOLD
A25L020C
DO
VSS
AMIC Technology Corp.


3Pages


A25L020C 電子部品, 半導体
OPERATING FEATURES
Page Programming
To program one data byte, two instructions are required: Write
Enable (WREN), which is one byte, and a Page Program (PP)
sequence, which consists of four bytes plus data. This is
followed by the internal Program cycle (of duration tPP).
To spread this overhead, the Page Program (PP) instruction
allows up to 256 bytes be programming at a time (changing
bits from 1 to 0), providing that they lie in consecutive
addresses on the same page of memory.
Sector Erase, Block Erase, and Chip Erase
The Page Program (PP) instruction allows bits to be reset
from 1 to 0. Before this can be applied, the bytes of memory
need to have been erased to all 1s (FFh). This can be
achieved, a sector at a time, using the Sector Erase (SE)
instruction, a block at a time, using the Block Erase (BE)
instruction, or throughout the entire memory, using the Chip
Erase (CE) instruction. This starts an internal Erase cycle (of
duration tSE, tBE, or tCE).
The Erase instruction must be preceded by a Write Enable
(WREN) instruction.
Polling During a Write, Program or Erase Cycle
A further improvement in the time to Write Status Register
(WRSR), Program (PP) or Erase (SE, BE, or CE) can be
achieved by not waiting for the worst case delay (tW, tPP, tSE,
tBE, tCE). The Write In Progress (WIP) bit is provided in the
Status Register so that the application program can monitor
its value, polling it to establish when the previous Write cycle,
Program cycle or Erase cycle is complete.
Active Power, Stand-by Power and Deep
Power-Down Modes
When Chip Select ( S ) is Low, the device is enabled, and in
the Active Power mode.
When Chip Select ( S ) is High, the device is disabled, but
could remain in the Active Power mode until all internal cycles
have completed (Program, Erase, Write Status Register). The
device then goes in to the Stand-by Power mode. The device
consumption drops to ICC1.
The Deep Power-down mode is entered when the specific
instruction (the Deep Power-down Mode (DP) instruction) is
executed. The device consumption drops further to ICC2. The
device remains in this mode until another specific instruction
(the Release from Deep Power-down Mode and Read
Electronic Signature (RES) instruction) is executed.
All other instructions are ignored while the device is in the
Deep Power-down mode. This can be used as an extra
software protection mechanism, when the device is not in
active use, to protect the device from inadvertent Write,
Program or Erase instructions.
A25L020C Series
Status Register
The Status Register contains a number of status and control
bits that can be read or set (as appropriate) by specific
instructions. See Read Status Register (RDSR) for a detailed
description of the Status Register bits.
Protection Modes
The environments where non-volatile memory devices are
used can be very noisy. No SPI device can operate correctly
in the presence of excessive noise. To help combat this, the
A25L020C boasts the following data protection mechanisms:
„ Power-On Reset and an internal timer (tPUW) can provide
protection against inadvertent changes while the power
supply is outside the operating specification.
„ Program, Erase and Write Status Register instructions are
checked that they consist of a number of clock pulses that
is a multiple of eight, before they are accepted for
execution.
„ All instructions that modify data must be preceded by a
Write Enable (WREN) instruction to set the Write Enable
Latch (WEL) bit. This bit is returned to its reset state by
the following events:
- Power-up
- Write Disable (WRDI) instruction completion
- Write Status Register (WRSR) instruction completion
- Page Program (PP) instruction completion
- Sector Erase (SE) instruction completion
- Block Erase (BE) instruction completion
- Chip Erase (CE) instruction completion
„ The Sector/Block Protect (SEC, BP2, BP1, BP0) bits allow
part of the memory to be configured as read-only. This is
the Software Protected Mode (SPM).
„ The Write Protect ( W ) signal allows the Sector/Block
Protect (SEC, BP2, BP1, BP0) bits and Status Register
Write Disable (SRWD) bit to be protected. This is the
Hardware Protected Mode (HPM).
„ In addition to the low power consumption feature, the
Deep Power-down mode offers extra software protection
from inadvertent Write, Program and Erase instructions,
as all instructions are ignored except one particular
instruction (the Release from Deep Power-down
instruction).
(December, 2014, Version 1.3)
5 AMIC Technology Corp.

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
A25L020

(A25L010 - A25L512) Serial Flash Memory

AMIC
AMIC
A25L020C

2Mbit 3V Serial Flash Memory

AMIC
AMIC


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