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Datasheet HCPL7710 PDF ( 特性, スペック, ピン接続図 )

部品番号 HCPL7710
部品説明 40 ns Propagation Delay / CMOS Optocoupler
メーカ Hewlett-Packard
ロゴ Hewlett-Packard ロゴ 
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Total 17 pages
		
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HCPL7710 Datasheet, HCPL7710 PDF,ピン配置, 機能
Agilent HCPL-7710, HCPL-0710
40 ns Propagation Delay,
CMOS Optocoupler
Data Sheet
Description
Available in either an 8-pin DIP or
SO-8 package style respectively,
the HCPL-7710 or HCPL-0710
optocouplers utilize the latest
CMOS IC technology to achieve
outstanding performance with
very low power consumption. The
HCPL-x710 require only two
bypass capacitors for complete
CMOS compatibility.
Basic building blocks of the
HCPL-x710 are a CMOS LED
driver IC, a high speed LED and a
CMOS detector IC. A CMOS logic
input signal controls the LED
driver IC which supplies current
to the LED. The detector IC
incorporates an integrated
photodiode, a high-speed
transimpedance amplifier, and a
voltage comparator with an
output driver.
Functional Diagram
**VDD1 1
VI 2
*3
GND1 4
LED1
SHIELD
8 VDD2**
7 NC*
IO
6 VO
TRUTH TABLE
(POSITIVE LOGIC)
VI, INPUT
H
L
LED1
OFF
ON
VO, OUTPUT
H
L
5 GND2
Features
• +5 V CMOS compatibility
• 8 ns maximum pulse width
distortion
• 20 ns maximum prop. delay skew
• High speed: 12 Mbd
• 40 ns maximum prop. delay
• 10 kV/µs minimum common mode
rejection
• -40°C to 100°C temperature range
• Safety and regulatory approvals
UL Recognized
3750 V rms for 1 min. per
UL 1577
CSA Component Acceptance
Notice #5
IEC/EN/DIN EN 60747-5-2
– VIORM = 630 Vpeak for
HCPL-7710 Option 060
– VIORM = 560 Vpeak for
HCPL-0710 Option 060
Applications
• Digital fieldbus isolation:
DeviceNet, SDS, Profibus
• AC plasma display panel level
shifting
• Multiplexed data transmission
• Computer peripheral interface
• Microprocessor system interface
* Pin 3 is the anode of the internal LED and must be left unconnected for guaranteed data sheet
performance. Pin 7 is not connected internally.
** A 0.1 µF bypass capacitor must be connected between pins 1 and 4, and 5 and 8.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this
component to prevent damage and/or degradation which may be induced by ESD.

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HCPL7710 pdf, ピン配列
Package Outline Drawing
HCPL-7710 Package with Gull Wing Surface Mount Option 300
9.65 ± 0.25
(0.380 ± 0.010)
87
65
LAND PATTERN RECOMMENDATION
1.016 (0.040)
6.350 ± 0.25
(0.250 ± 0.010)
10.9 (0.430)
12
34
1.19
(0.047)
MAX.
1.780
(0.070)
MAX.
3.56 ± 0.13
(0.140 ± 0.005)
1.27 (0.050)
9.65 ± 0.25
(0.380 ± 0.010)
7.62 ± 0.25
(0.300 ± 0.010)
2.0 (0.080)
+ 0.076
0.254 - 0.051
+ 0.003)
(0.010 - 0.002)
1.080 ± 0.320
(0.043 ± 0.013)
2.54
(0.100)
BSC
0.635 ± 0.130
(0.025 ± 0.005)
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
0.635 ± 0.25
(0.025 ± 0.010)
NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX.
12° NOM.
Package Outline Drawing
HCPL-0710 Outline Drawing (Small Outline SO-8 Package)
LAND PATTERN RECOMMENDATION
8
3.937 ± 0.127
(0.155 ± 0.005)
PIN ONE 1
0.406 ± 0.076
(0.016 ± 0.003)
765
XXXV
YWW
234
5.994 ± 0.203
(0.236 ± 0.008)
TYPE NUMBER
(LAST 3 DIGITS)
DATE CODE
1.270 BSC
(0.050)
7.49 (0.295)
1.9 (0.075)
0.64 (0.025)
* 5.080 ± 0.127
(0.200 ± 0.005)
7°
45°
X
0.432
(0.017)
3.175 ± 0.127
(0.125 ± 0.005)
1.524
(0.060)
0 ~ 7°
0.228 ± 0.025
(0.009 ± 0.001)
* TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH)
5.207 ± 0.254 (0.205 ± 0.010)
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX.
0.203 ± 0.102
(0.008 ± 0.004)
0.305 MIN.
(0.012)
OPTION NUMBER 500 NOT MARKED.
NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.
3


3Pages


HCPL7710 電子部品, 半導体
Electrical Specifications
Test conditions that are not specified can be anywhere within the recommended operating range. All typical specifications
are at TA = +25°C, VDD1 = VDD2 = +5 V.
Parameter
Symbol Min.
Typ. Max. Units Test Conditions
Fig. Note
DC Specifications
Logic Low Input
Supply Current
IDD1L
6.0
10.0 mA
VI = 0 V
1
Logic High Input
Supply Current
IDD1H
1.5
3.0 mA
VI = VDDI
Input Supply Current
Output Supply Current
Input Current
Logic High Output
Voltage
Logic Low Output
Voltage
Switching Specifications
IDD1
IDD2
II
VOH
VOL
-10
4.4
4.0
13.0 mA
5.5 11.0 mA
10 µA
5.0 V
4.8
0 0.1 V
0.5 1.0
IO = -20 µA, VI = VIH
IO = -4 mA, VI = VIH
IO = 20 µA, VI = VIL
IO = 4 mA, VI = VIL
1, 2
Propagation Delay Time
to Logic Low Output
tPHL
20
40 ns
CL = 15 pF
3, 7 2
CMOS Signal Levels
Propagation Delay Time
to Logic High Output
tPLH
23 40
Pulse Width
PW 80
3
Data Rate
12.5 MBd
Pulse Width Distortion
|tPHL - tPLH|
Propagation Delay Skew
Output Rise Time
(10 - 90%)
PWD
tPSK
tR
3 8 ns
20
9
4, 8 4
5
5, 9
Output Fall Time
(90 - 10%)
tF
8
6,
10
Common Mode
Transient Immunity at
Logic High Output
Common Mode
Transient Immunity at
Logic Low Output
|CMH| 10
|CML| 10
20
20
kV/µs
VI = VDD1, VO >
0.8 VDD1,
VCM = 1000 V
VI = 0 V, VO > 0.8 V,
VCM = 1000 V
6
Input Dynamic Power
Dissipation
Capacitance
CPD1
60 pF
7
Output Dynamic Power
Dissipation
Capacitance
CPD2
10
6

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