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HCPL7710 データシート PDF ( 特性, スペック, ピン接続図 )

部品番号 HCPL7710
部品説明 40 ns Propagation Delay / CMOS Optocoupler
メーカ Hewlett-Packard
ロゴ Hewlett-Packard ロゴ 

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HCPL7710 Datasheet, HCPL7710 PDF,ピン配置, 機能
Agilent HCPL-7710, HCPL-0710
40 ns Propagation Delay,
CMOS Optocoupler
Data Sheet
Description
Available in either an 8-pin DIP or
SO-8 package style respectively,
the HCPL-7710 or HCPL-0710
optocouplers utilize the latest
CMOS IC technology to achieve
outstanding performance with
very low power consumption. The
HCPL-x710 require only two
bypass capacitors for complete
CMOS compatibility.
Basic building blocks of the
HCPL-x710 are a CMOS LED
driver IC, a high speed LED and a
CMOS detector IC. A CMOS logic
input signal controls the LED
driver IC which supplies current
to the LED. The detector IC
incorporates an integrated
photodiode, a high-speed
transimpedance amplifier, and a
voltage comparator with an
output driver.
Functional Diagram
**VDD1 1
VI 2
*3
GND1 4
LED1
SHIELD
8 VDD2**
7 NC*
IO
6 VO
TRUTH TABLE
(POSITIVE LOGIC)
VI, INPUT
H
L
LED1
OFF
ON
VO, OUTPUT
H
L
5 GND2
Features
• +5 V CMOS compatibility
• 8 ns maximum pulse width
distortion
• 20 ns maximum prop. delay skew
• High speed: 12 Mbd
• 40 ns maximum prop. delay
• 10 kV/µs minimum common mode
rejection
• -40°C to 100°C temperature range
• Safety and regulatory approvals
UL Recognized
3750 V rms for 1 min. per
UL 1577
CSA Component Acceptance
Notice #5
IEC/EN/DIN EN 60747-5-2
– VIORM = 630 Vpeak for
HCPL-7710 Option 060
– VIORM = 560 Vpeak for
HCPL-0710 Option 060
Applications
• Digital fieldbus isolation:
DeviceNet, SDS, Profibus
• AC plasma display panel level
shifting
• Multiplexed data transmission
• Computer peripheral interface
• Microprocessor system interface
* Pin 3 is the anode of the internal LED and must be left unconnected for guaranteed data sheet
performance. Pin 7 is not connected internally.
** A 0.1 µF bypass capacitor must be connected between pins 1 and 4, and 5 and 8.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this
component to prevent damage and/or degradation which may be induced by ESD.

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