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MTP6N60EのメーカーはON Semiconductorです、この部品の機能は「Power Field Effect Transistor」です。 |
部品番号 | MTP6N60E |
| |
部品説明 | Power Field Effect Transistor | ||
メーカ | ON Semiconductor | ||
ロゴ | |||
このページの下部にプレビューとMTP6N60Eダウンロード(pdfファイル)リンクがあります。 Total 8 pages
MTP6N60E
Power Field Effect
Transistor
N−Channel Enhancement−Mode Silicon
Gate
This high voltage MOSFET uses an advanced termination scheme
to provide enhanced voltage−blocking capability without degrading
performance over time. In addition, this advanced MOSFET is
designed to withstand high energy in the avalanche and commutation
modes. The new energy efficient design also offers a drain−to−source
diode with a fast recovery time. Designed for high voltage, high speed
switching applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are critical
and offer additional safety margin against unexpected voltage
transients.
• Robust High Voltage Termination
• Avalanche Energy Specified
• Source−to−Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature
http://onsemi.com
TMOS POWER FET
6.0 AMPERES, 600 VOLTS
RDS(on) = 1.2 W
TO−220AB
CASE 221A−09
Style 5
D
G
S
© Semiconductor Components Industries, LLC, 2013
May, 2013 − Rev. 7
1
Publication Order Number:
MTP6N60E/D
1 Page MTP6N60E
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 μAdc)
Temperature Coefficient (Positive)
V(BR)DSS
600
−
− 689
− Vdc
− mV/°C
Zero Gate Voltage Drain Current
(VDS = 600 Vdc, VGS = 0 Vdc)
(VDS = 600 Vdc, VGS = 0 Vdc, TJ = 125°C)
Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc)
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 μAdc)
Temperature Coefficient (Negative)
IDSS
IGSS
VGS(th)
μAdc
− − 1.0
− − 50
− − 100 nAdc
2.0 3.0 4.0 Vdc
− 7.1 − mV/°C
Static Drain−to−Source On−Resistance (VGS = 10 Vdc, ID = 3.0 Adc)
Drain−to−Source On−Voltage
(VGS = 10 Vdc, ID = 6.0 Adc)
(VGS = 10 Vdc, ID = 3.0 Adc, TJ = 125°C)
Forward Transconductance (VDS = 15 Vdc, ID = 3.0 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
SWITCHING CHARACTERISTICS (2)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
(VDS = 300 Vdc, ID = 6.0 Adc,
VGS = 10 Vdc,
RG = 9.1 Ω)
Gate Charge
(VDS = 300 Vdc, ID = 6.0 Adc,
VGS = 10 Vdc)
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage (1)
(IS = 6.0 Adc, VGS = 0 Vdc)
(IS = 6.0 Adc, VGS = 0 Vdc, TJ = 125°C)
RDS(on)
VDS(on)
gFS
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
QT
Q1
Q2
Q3
VSD
− 0.94 1.2 Ohms
Vdc
− 6.0 8.6
− − 7.6
2.0 5.5
− mhos
−
1498
2100
pF
− 158 220
− 29 60
− 14 30 ns
− 19 40
− 40 80
− 26 55
− 35.5 50 nC
− 8.1 −
− 14.1 −
− 15.8 −
Vdc
− 0.83 1.2
− 0.72 −
Reverse Recovery Time
(IS = 6.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/μs)
Reverse Recovery Stored Charge
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25″ from package to center of die)
trr
ta
tb
QRR
LD
− 266 −
ns
− 166 −
− 100 −
− 2.5 − μC
nH
− 3.5 −
− 4.5 −
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
(1) Pulse Test: Pulse Width ≤ 300 μs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
LS
− nH
− 7.5
http://onsemi.com
3
3Pages MTP6N60E
12 300
QT
10
8
6 Q1
VGS 200
Q2
4 ID = 6 A 100
2 TJ = 25°C
Q3 VDS
00
0 6 12 18 24 30 36
QT, TOTAL CHARGE (nC)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
1000
VDD = 300 V
ID = 6 A
VGS = 10 V
TJ = 25°C
100
td(off)
tf
10
tr
td(on)
1
1 10 100
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
6
VGS = 0 V
5 TJ = 25°C
4
3
2
1
0
0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85
VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal
Resistance−General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 μs. In addition the total
power averaged over a complete switching cycle must not
exceed (TJ(MAX) − TC)/(RθJC).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 12). Maximum
energy at currents below rated continuous ID can safely be
assumed to equal the values indicated.
http://onsemi.com
6
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