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PDF MTD15N06V Data sheet ( Hoja de datos )
| Número de pieza | MTD15N06V | |
| Descripción | Power MOSFET ( Transistor ) | |
| Fabricantes | ON Semiconductor | |
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MTD15N06V
Preferred Device
Power MOSFET
15 Amps, 60 Volts
N−Channel DPAK
This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and power
motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected voltage
transients.
• Avalanche Energy Specified
• IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain−Source Voltage
Drain−Gate Voltage (RGS = 1.0 MΩ)
Gate−Source Voltage
− Continuous
− Single Pulse (tp ≤ 50 ms)
Drain Current − Continuous @ 25°C
Drain Current − Continuous @ 100°C
Drain Current − Single Pulse (tp ≤ 10 μs)
Total Power Dissipation @ 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C (Note 2)
Operating and Storage Temperature Range
VDSS
VDGR
VGS
VGSM
ID
ID
IDM
PD
TJ, Tstg
60 Vdc
60 Vdc
± 20
± 25
15
8.7
45
55
0.36
2.1
−55 to
175
Vdc
Vpk
Adc
Apk
Watts
W/°C
Watts
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc,
IL = 15 Apk, L = 1.0 mH, RG = 25 Ω)
EAS 113 mJ
Thermal Resistance
− Junction to Case
− Junction to Ambient (Note 1)
− Junction to Ambient (Note 2)
RθJC
RθJA
RθJA
°C/W
2.73
100
71.4
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
TL 260 °C
1. When surface mounted to an FR4 board using the minimum recommended
pad size.
2. When surface mounted to an FR4 board using 0.5 sq. in. drain pad size.
http://onsemi.com
V(BR)DSS
60 V
RDS(on) TYP
80 mW
ID MAX
15 A
N−Channel
D
G
4
12
3
DPAK
CASE 369C
Style 2
4
S
MARKING DIAGRAMS
4
Drain
1
Gate
2
Drain
3
Source
4
Drain
1 23
DPAK
CASE 369D
Style 2
15N06V
Y
WW
Device Code
= Year
= Work Week
12 3
Gate Drain Source
ORDERING INFORMATION
Device
Package
Shipping
MTD15N06V
MTD15N06V−1
MTD15N06VT4
DPAK
DPAK
Straight Lead
DPAK
75 Units/Rail
75 Units/Rail
2500 Tape &
Reel
© Semiconductor Components Industries, LLC, 2006
August, 2006 − Rev. 5
1
Publication Order Number:
MTD15N06V/D
1 page  
MTD15N06V
12
10
8
Q1
6
QT
Q2
VGS
60
50
40
30
4 20
ID = 15 A
2 TJ = 25°C 10
0 Q3
VDS
0
0 3 6 9 12 15
QT, TOTAL CHARGE (nC)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
1000
100
10
VDD = 30 V
ID = 15 A
VGS = 10 V
TJ = 25°C
tr
tf
td(off)
td(on)
1
1 10
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
15
VGS = 0 V
TJ = 25°C
12
100
9
6
3
0
0.5 0.7 0.9 1.1 1.3 1.5
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal
Resistance−General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 μs. In addition the total
power averaged over a complete switching cycle must not
exceed (TJ(MAX) − TC)/(RθJC).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 12). Maximum
energy at currents below rated continuous ID can safely be
assumed to equal the values indicated.
http://onsemi.com
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| PDF Descargar | [ Datasheet MTD15N06V.PDF ] | |
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