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R5F51303AGFK の電気的特性と機能

R5F51303AGFKのメーカーはRenesasです、この部品の機能は「32-bit RX MCUs」です。


製品の詳細 ( Datasheet PDF )

部品番号 R5F51303AGFK
部品説明 32-bit RX MCUs
メーカ Renesas
ロゴ Renesas ロゴ 




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R5F51303AGFK Datasheet, R5F51303AGFK PDF,ピン配置, 機能
Datasheet
RX130 Group
Renesas MCUs
32-MHz, 32-bit RX MCUs, 50 DMIPS, up to 128-KB flash memory,
R01DS0273EJ0100
Rev.1.00
Oct 30, 2015
up to 36 pins capacitive touch sensing unit, up to 6 comms channels, 12-bit A/D, D/A, RTC,
IEC60730 compliance, 1.8-V to 5.5-V single supply
Features
32-bit RX CPU core
Max. operating frequency: 32 MHz
Capable of 50 DMIPS in operation at 32 MHz
Accumulator handles 64-bit results (for a single instruction) from
32-bit × 32-bit operations
Multiplication and division unit handles 32-bit × 32-bit operations
(multiplication instructions take one CPU clock cycle)
Fast interrupt
CISC Harvard architecture with 5-stage pipeline
Variable-length instructions, ultra-compact code
On-chip debugging circuit
Low power design and architecture
Operation from a single 1.8-V to 5.5-V supply
Three low power consumption modes
Low power timer (LPT) that operates during the software standby state
Supply current
High-speed operating mode: 96 A/MHz
Supply current in software standby mode: 0.37 A
Recovery time from software standby mode: 4.8 s
On-chip flash memory for code, no wait states
Operation at 32 MHz, read cycle of 31.25 ns
No wait states for reading at full CPU speed
Programmable at 1.8 V
For instructions and operands
On-chip data flash memory
8 Kbytes (1,000,000 program/erase cycles (typ.))
BGO (Background Operation)
On-chip SRAM, no wait states
10- to 16-Kbyte size capacities
DTC
Four transfer modes
Transfer can be set for each interrupt source.
ELC
Module operation can be initiated by event signals without using
interrupts.
Linked operation between modules is possible while the CPU is sleeping.
Reset and supply management
Eight types of reset, including the power-on reset (POR)
Low voltage detection (LVD) with voltage settings
Clock functions
External clock input frequency: Up to 20 MHz
Main clock oscillator frequency: 1 to 20 MHz
Sub clock oscillator frequency: 32.768 kHz
PLL circuit input: 4 MHz to 8 MHz
Low-speed on-chip oscillator: 4 MHz
High-speed on-chip oscillator: 32 MHz ± 1 %
IWDT-dedicated on-chip oscillator: 15 kHz
Generate a 32.768 kHz clock for the real-time clock
On-chip clock frequency accuracy measurement circuit (CAC)
Realtime clock
Adjustment functions (30 seconds, leap year, and error)
Calendar count mode or binary count mode selectable
Independent watchdog timer
15-kHz on-chip oscillator produces a dedicated clock signal to drive
IWDT operation.
Useful functions for IEC60730 compliance
Self-diagnostic and disconnection-detection assistance functions for
the A/D converter, clock frequency accuracy measurement circuit,
independent watchdog timer, RAM test assistance functions using the
DOC, etc.
PLQP0080KB-B 12 × 12mm, 0.5mm pitch
PLQP0064GA-A 14 × 14mm, 0.8mm pitch
PLQP0064KB-C 10 × 10mm, 0.5mm pitch
PLQP0048KB-B 7 × 7mm, 0.5mm pitch
PWQN0048KB-A 7 × 7mm, 0.5mm pitch
MPC
Input/output functions selectable from multiple pins
Up to 6 communication functions
SCI with many useful functions (up to 4 channels)
Asynchronous mode (Fine adjustable baud rate: 0 to 255/255), clock
synchronous mode, smart card interface mode
I2C bus interface: Transfer at up to 400 kbps, capable of SMBus
operation (one channel)
RSPI (one channel): Transfer at up to 16 Mbps
Up to 12 extended-function timersMPC
16-bit MTU: input capture, output compare, complementary PWM
output, phase counting mode (six channels)
8-bit TMR (four channels)
16-bit compare-match timers (two channels)
12-bit A/D converter
Capable of conversion within 1.4 μs
17 channels
Sampling time can be set for each channel
Conversion results compare features
Self-diagnostic function and analog input disconnection detection
assistance function
Double trigger (data duplication) function for motor control
D/A converter
Two channels
Capacitive touch sensing unit
Self-capacitance method: A single pin configures a single key,
supporting up to 36 keys
Mutual capacitance method: Matrix configuration with 36pins, supporting
up to 324 keys
Comparator B
Two channels
General I/O ports
5-V tolerant, open drain, input pull-up, switching of driving capacity
Temperature sensor
Unique ID
32-byte ID code for the MCU
Operating temperature range
 40 to +85C
 40 to +105C
Applications
General industrial and consumer equipment
R01DS0273EJ0100 Rev.1.00
Oct 30, 2015
Page 1 of 116

1 Page





R5F51303AGFK pdf, ピン配列
RX130 Group
1. Overview
Table 1.1
Outline of Specifications (2/3)
Classification
DMA
Module/Function
Data transfer controller
(DTCa)
I/O ports
General I/O ports
Event link controller (ELC)
Multi-function pin controller (MPC)
Timers
Multi-function timer pulse
unit 2 (MTU2a)
Port output enable 2
(POE2a)
Compare match timer
(CMT)
Independent watchdog
timer (IWDTa)
Realtime clock (RTCc)
Low power timer (LPT)
8-bit timer (TMR)
Communication
functions
Serial communications
interfaces (SCIg, SCIh)
I2C bus interface (RIICa)
Description
Transfer modes: Normal transfer, repeat transfer, and block transfer
Activation sources: Interrupts
Chain transfer function
80-pin /64-pin /48-pin
I/O: 68/52/38
Input: 1/1/1
Pull-up resistors: 68/52/38
Open-drain outputs: 47/35/26
5-V tolerance: 4/2/2
Event signals of 47 types can be directly connected to the module
Operations of timer modules are selectable at event input
Capable of event link operation for port B
Capable of selecting the input/output function from multiple pins
(16 bits × 6 channels) × 1 unit
Up to 16 pulse-input/output lines and three pulse-input lines are available based on the six 16-bit
timer channels
Select from among eight or seven counter-input clock signals for each channel (PCLK/1, PCLK/4,
PCLK/16, PCLK/64, PCLK/256, PCLK/1024, MTCLKA, MTCLKB, MTCLKC, MTCLKD) other than
channel 5, for which only four signals are available.
Input capture function
21 output compare/input capture registers
Pulse output mode
Complementary PWM output mode
Reset synchronous PWM mode
Phase-counting mode
Capable of generating conversion start triggers for the A/D converter
Controls the high-impedance state of the MTU’s waveform output pins
(16 bits × 2 channels) × 1 unit
Select from among four clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512)
14 bits × 1 channel
Count clock: Dedicated low-speed on-chip oscillator for the IWDT
Frequency divided by 1, 16, 32, 64, 128, or 256
Clock source: Sub-clock
Calendar count mode or binary count mode selectable
Interrupts: Alarm interrupt, periodic interrupt, and carry interrupt
16 bits × 1 channel
Clock source: Sub-clock, Dedicated low-speed on-chip oscillator for the IWDT
Frequency divided by 2, 4, 8, 16, or 32
(8 bits × 2 channels) × 2 units
Seven internal clocks (PCLK/1, PCLK/2, PCLK/8, PCLK/32, PCLK/64, PCLK/1024, and PCLK/8192)
and an external clock can be selected
Pulse output and PWM output with any duty cycle are available
Two channels can be cascaded and used as a 16-bit timer
4 channels (channel 1, 5, 6: SCIg, channel 12: SCIh)
SCIg
Serial communications modes: Asynchronous, clock synchronous, and smart-card interface
On-chip baud rate generator allows selection of the desired bit rate
Choice of LSB-first or MSB-first transfer
Average transfer rate clock can be input from TMR timers for SCI5, SCI6, and SCI12
Start-bit detection: Level or edge detection is selectable.
Simple I2C
Simple SPI
9-bit transfer mode
Bit rate modulation
Event linking by the ELC (only on channel 5)
SCIh (The following functions are added to SCIg)
Supports the serial communications protocol, which contains the start frame and information frame
Supports the LIN format
1 channel
Communications formats: I2C bus format/SMBus format
Master mode or slave mode selectable
Supports fast mode
R01DS0273EJ0100 Rev.1.00
Oct 30, 2015
Page 3 of 116


3Pages


R5F51303AGFK 電子部品, 半導体
RX130 Group
1. Overview
1.2 List of Products
Table 1.3 is a lists of products, and Figure 1.1 shows how to read the product part no., memory capacity, and package
type.
Table 1.3
List of Products
Group
RX130
Part No.
R5F51305ADFN
R5F51305ADFM
R5F51305ADFK
R5F51305ADFL
R5F51305ADNE
R5F51303ADFN
R5F51303ADFM
R5F51303ADFK
R5F51303ADFL
R5F51303ADNE
R5F51305AGFN
R5F51305AGFM
R5F51305AGFK
R5F51305AGFL
R5F51305AGNE
R5F51303AGFN
R5F51303AGFM
R5F51303AGFK
R5F51303AGFL
R5F51303AGNE
Orderable Part No.
R5F51305ADFN#30
R5F51305ADFM#30
R5F51305ADFK#30
R5F51305ADFL#30
R5F51305ADNE#U0
R5F51303ADFN#30
R5F51303ADFM#30
R5F51303ADFK#30
R5F51303ADFL#30
R5F51303ADNE#U0
R5F51305AGFN#30
R5F51305AGFM#30
R5F51305AGFK#30
R5F51305AGFL#30
R5F51305AGNE#U0
R5F51303AGFN#30
R5F51303AGFM#30
R5F51303AGFK#30
R5F51303AGFL#30
R5F51303AGNE#U0
Package
PLQP0080KB-B
PLQP0064KB-C
PLQP0064GA-A
PLQP0048KB-B
PWQN0048KB-A
PLQP0080KB-B
PLQP0064KB-C
PLQP0064GA-A
PLQP0048KB-B
PWQN0048KB-A
PLQP0080KB-B
PLQP0064KB-C
PLQP0064GA-A
PLQP0048KB-B
PWQN0048KB-A
PLQP0080KB-B
PLQP0064KB-C
PLQP0064GA-A
PLQP0048KB-B
PWQN0048KB-A
ROM
Capacity
RAM
Capacity
E2
DataFlash
Maximum
Operating
Frequency
Operating
Temperature
128 Kbytes 16 Kbytes
40 to 85°C
64 Kbytes 10 Kbytes
8 Kbytes
32 MHz
128 Kbytes 16 Kbytes
40 to 105°C
64 Kbytes 10 Kbytes
R01DS0273EJ0100 Rev.1.00
Oct 30, 2015
Page 6 of 116

6 Page



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部品番号部品説明メーカ
R5F51303AGFK

32-bit RX MCUs

Renesas
Renesas
R5F51303AGFL

32-bit RX MCUs

Renesas
Renesas
R5F51303AGFM

32-bit RX MCUs

Renesas
Renesas
R5F51303AGFN

32-bit RX MCUs

Renesas
Renesas


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