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R5F5110JADFM の電気的特性と機能

R5F5110JADFMのメーカーはRenesasです、この部品の機能は「32 MHz 32-bit RX MCUs」です。


製品の詳細 ( Datasheet PDF )

部品番号 R5F5110JADFM
部品説明 32 MHz 32-bit RX MCUs
メーカ Renesas
ロゴ Renesas ロゴ 




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R5F5110JADFM Datasheet, R5F5110JADFM PDF,ピン配置, 機能
Datasheet
RX110 Group
Renesas MCUs
R01DS0202EJ0110
Rev.1.10
Dec 10, 2014
32 MHz 32-bit RX MCUs, 50 DMIPS,
up to 128 Kbytes of flash memory, up to 5 comms channels, 12-bit A/D, RTC
Features
32-bit RX CPU core
32 MHz maximum operating frequency
Capable of 50 DMIPS when operating at 32 MHz
Accumulator handles 64-bit results (for a single
instruction) from 32-bit × 32-bit operations
Multiplication and division unit handles 32-bit × 32-bit
operations (multiplication instructions take one CPU
clock cycle)
Fast interrupt
CISC Harvard architecture with five-stage pipeline
Variable-length instruction format, ultra-compact code
On-chip debugging circuit
Low power consumption functions
Operation from a single 1.8 to 3.6 V supply
Three low power modes
Supply current
High-speed operating mode: 0.1 mA/MHz
Software standby mode: 0.35 μA
Recovery time from software standby mode: 4.8 μs
On-chip flash memory for code, no wait states
Operation at 32 MHz, read cycle of 31.25 ns
No wait states for reading at full CPU speed
8 to 128 Kbyte capacities
Programmable at 1.8 V
For instructions and operands
On-chip SRAM, no wait states
8 to 16 Kbyte capacities
Data transfer controller (DTC)
Four transfer modes
Transfer can be set for each interrupt source.
Reset and power supply voltage management
Six types including the power-on reset (POR)
Low voltage detection (LVD) with voltage settings
Clock functions
External clock input frequency: Up to 20 MHz
Main clock oscillator frequency: 1 to 20 MHz
Sub-clock oscillator frequency: 32.768 kHz
Low-speed on-chip oscillator: 4 MHz
High-speed on-chip oscillator: 32 MHz±1% (20 to 85°C)
IWDT-dedicated on-chip oscillator: 15 kHz
Generate a dedicated 32.768-kHz clock for the RTC
On-chip clock frequency accuracy measurement circuit
(CAC)
Real-time clock (RTC)
30-second, leap year, and error adjustment functions
Calendar count mode or binary count mode selectable
Capable initiating exit from software standby mode
R01DS0202EJ0110 Rev.1.10
Dec 10, 2014
PLQP0064KB-A 10 × 10 mm, 0.5 mm pitch
PLQP0064GA-A 14 × 14 mm, 0.8 mm pitch
PLQP0048KB-A 7 × 7 mm, 0.5 mm pitch
PWQN0048KB-A 7 × 7 mm, 0.5 mm pitch
PWQN0040KC-A 6 × 6 mm, 0.5 mm pitch
PWLG0064KA-A 5 × 5 mm, 0.5 mm pitch
PWLG0036KA-A 4 × 4 mm, 0.5 mm pitch
Independent watchdog timer (WDT)
15-kHz on-chip oscillator produces a dedicated clock
signal to drive IWDT operation.
On-chip functions for IEC 60730 compliance
Clock frequency accuracy measurement circuit, IWDT,
functions to assist in RAM testing, etc.
Up to five channels for communication
SCI: Asynchronous mode, clock synchronous mode,
smart card interface (up to seven channels)
I2C bus interface: Transfer at up to 400 kbps, capable of
SMBus operation (one channel)
RSPI: Up to 16 Mbps (one channel)
Up to 6 extended-function timers
16-bit MTU: Input capture/output compare,
phase counting mode (four channels)
16-bit CMT (two channels)
12-bit A/D converter
Up to 14 channels
1.0 μs minimum conversion speed
Double trigger (data duplication) function for motor
control
Temperature sensor
General I/O ports
5-V tolerant, open drain, input pull-up
Multi-function pin controller (MPC)
Multiple I/O pins can be selected for peripheral functions.
Unique ID
32-byte ID code for the MCU
Operating temperature range
 40 to 85C
 40 to 105°C
Page 1 of 103

1 Page





R5F5110JADFM pdf, ピン配列
RX110 Group
1. Overview
Table 1.1
Outline of Specifications (2/3)
Classification
I/O ports
Module/Function
General I/O ports
Multi-function pin controller (MPC)
Timers
Multi-function timer pulse
unit 2 (MTU2b)
Compare match timer
(CMT)
Independent watchdog
timer (IWDTa)
Realtime clock (RTCA)
Communication
functions
Serial communications
interfaces (SCIe, SCIf)
I2C bus interface (RIIC)
Serial peripheral interface
(RSPI)
12-bit A/D converter (S12ADb)
Temperature sensor (TEMPSA)
CRC calculator (CRC)
Description
64-pin /48-pin /40-pin /36-pin
I/O: 50/34/28/24
Input: 2/2/1/1
Pull-up resistors: 42/28/23/20
Open-drain outputs: 38/28/23/20
5-V tolerance: 4/4/4/4
Capable of selecting the input/output function from multiple pins
(16 bits × 4 channels) × 1 unit
Time bases for the four 16-bit timer channels can be provided via up to 8 pulse-input/output lines and
three pulse-input lines
Select from among eight or seven counter-input clock signals for each channel (PCLK/1, PCLK/4,
PCLK/16, PCLK/64, PCLK/256, PCLK/1024, MTCLKA, MTCLKB, MTCLKC, MTCLKD) other than
channel 5, for which only four signals are available.
Input capture function
13 output compare/input capture registers
Pulse output mode
Phase counting mode
Generation of triggers for A/D converter conversion
(16 bits × 2 channels) × 1 unit
Select from among four clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512)
14 bits × 1 channel
Count clock: Dedicated low-speed on-chip oscillator for the IWDT
Frequency divided by 1, 16, 32, 64, 128, or 256
Clock source: Sub-clock
Calendar count mode or binary count mode selectable
Interrupts: Alarm interrupt, periodic interrupt, and carry interrupt
3 channels (channel 1, 5: SCIe, channel 12: SCIf)
Serial communications modes: Asynchronous, clock synchronous, and smart card interface
On-chip baud rate generator allows selection of the desired bit rate
Choice of LSB first or MSB first transfer
Average transfer rate clock can be input from MTU2 timers
Simple I2C
Simple SPI
Master/slave mode supported (SCIf only)
Start frame and information frame are included (SCIf only)
Start-bit detection in asynchronous mode: Low level or falling edge is selectable (SCIe/SCIf)
1 channel
Communications formats:
I2C bus format/SMBus format
Master mode or slave mode selectable
Supports fast mode
1 channel
Transfer facility
Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select), and RSPI
clock (RSPCK) signals enables serial transfer through SPI operation (four lines) or clock-
synchronous operation (three lines)
Capable of handling serial transfer as a master or slave
Data formats
Choice of LSB first or MSB first transfer
The number of bits in each transfer can be changed to 8, 9, 10, 11, 12, 13, 14, 15, 16, 20, 24, or
32 bits.
128-bit buffers for transmission and reception
Up to four frames can be transmitted or received in a single transfer operation (with each frame
having up to 32 bits)
Double buffers for both transmission and reception
1 unit (1 unit × 14 channels)
12-bit resolution
Minimum conversion time: 1.0 µs per channel when the ADCLK is operating at 32 MHz
Operating modes
Scan mode (single scan mode, continuous scan mode, and group scan mode)
Double trigger mode (duplication of A/D conversion data)
A/D conversion start conditions
A software trigger, a trigger from a timer (MTU), or an external trigger signal
1 channel
The voltage of the temperature is converted into a digital value by the 12-bit A/D converter.
CRC code generation for arbitrary amounts of data in 8-bit units
Select any of three generating polynomials:
X8 + X2 + X + 1, X16 + X15 + X2 + 1, or X16 + X12 + X5 + 1
Generation of CRC codes for use with LSB first or MSB first communications is selectable.
R01DS0202EJ0110 Rev.1.10
Dec 10, 2014
Page 3 of 103


3Pages


R5F5110JADFM 電子部品, 半導体
RX110 Group
1. Overview
1.2 List of Products
Table 1.3 is a list of products, and Figure 1.1 shows how to read the product part no., memory capacity, and package
type.
Table 1.3
List of Products (1/2)
Group
RX110
Part No.
R5F51105AGFM
R5F51105AGFK
R5F51105AGFL
R5F51105AGNE
R5F51104AGFM
R5F51104AGFK
R5F51104AGFL
R5F51104AGNE
R5F51103AGFM
R5F51103AGFK
R5F51103AGFL
R5F51103AGNE
R5F51103AGNF
R5F51101AGFM
R5F51101AGFK
R5F51101AGFL
R5F51101AGNE
R5F51101AGNF
R5F5110JAGFM
R5F5110JAGFK
R5F5110JAGFL
R5F5110JAGNE
R5F5110JAGNF
R5F5110HAGNF
Orderable Part No.
R5F51105AGFM#30
R5F51105AGFK#30
R5F51105AGFL#30
R5F51105AGNE#U0
R5F51104AGFM#30
R5F51104AGFK#30
R5F51104AGFL#30
R5F51104AGNE#U0
R5F51103AGFM#30
R5F51103AGFK#30
R5F51103AGFL#30
R5F51103AGNE#U0
R5F51103AGNF#U0
R5F51101AGFM#30
R5F51101AGFK#30
R5F51101AGFL#30
R5F51101AGNE#U0
R5F51101AGNF#U0
R5F5110JAGFM#30
R5F5110JAGFK#30
R5F5110JAGFL#30
R5F5110JAGNE#U0
R5F5110JAGNF#U0
R5F5110HAGNF#U0
Package
PLQP0064KB-A
PLQP0064GA-A
PLQP0048KB-A
PWQN0048KB-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0048KB-A
PWQN0048KB-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0048KB-A
PWQN0048KB-A
PWQN0040KC-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0048KB-A
PWQN0048KB-A
PWQN0040KC-A
PLQP0064KB-A
PLQP0064GA-A
PLQP0048KB-A
PWQN0048KB-A
PWQN0040KC-A
PWQN0040KC-A
ROM
Capacity
128 Kbytes
96 Kbytes
64 Kbytes
32 Kbytes
16 Kbytes
8 Kbytes
RAM
Capacity
16 Kbytes
10 Kbytes
8 Kbytes
Maximum
Operating
Frequency
32 MHz
Operating
Temperature
40 to +105°C
R01DS0202EJ0110 Rev.1.10
Dec 10, 2014
Page 6 of 103

6 Page



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部品番号部品説明メーカ
R5F5110JADFK

32 MHz 32-bit RX MCUs

Renesas
Renesas
R5F5110JADFL

32 MHz 32-bit RX MCUs

Renesas
Renesas
R5F5110JADFM

32 MHz 32-bit RX MCUs

Renesas
Renesas


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