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PDF PL502-38 Data sheet ( Hoja de datos )
| Número de pieza | PL502-38 | |
| Descripción | 750kHz - 800MHz Low Phase Noise Multiplier VCXO | |
| Fabricantes | Micrel | |
| Logotipo |  |
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PL502-35/-37/-38/-39
750kHz – 800MHz Low Phase Noise Multiplier VCXO
Universal Low Phase Noise ICs
FEATURES
PIN CONFIGURATION
Selectable 750kHz to 800MHz range
Low phase noise output (@ 10kHz frequency off-
set, -142dBc/Hz for 19.44MHz, -125dBc/Hz for
155.52MHz, -115dBc/Hz for 622.08MHz)
LVCMOS (PL502-37), LVPECL (PL502-35 and
PL502-38) or LVDS (PL502-39) output
12MHz to 25MHz crystal input
No external load capacitor or varicap required.
Output Enable selector
Wide pull range (±200 ppm)
Selectable /16 to x32 frequency divider/multiplier
3.3V operation
Available in 16-Pin TSSOP or 16-pin 3x3mm QFN
GREEN/RoHS compliant packages
(Top View)
VDD
XIN
XOUT
SEL3^
SEL2^
OE
VCON
GND
1
2
3
4
5
6
7
8
1
6
SEL0^
1
5
SEL1^
1
4
GND
1
3
CLKC
1
2
VDD
1
1
CLKT
1
0
GND
9 GND
TSSOP-16L
^: Internal pull-up
*: On 3x3 package, PL502-35/-38 do not have SEL0 available: Pin 10
is VDD, pin 11 is GND. However, PL502-37/-39 have SEL0 (pin 10),
and pin11 is VDD. See pin assignment table for details.
DESCRIPTION
The PL502-35 (LVPECL with inverted OE), PL502-37
(LVCMOS), PL502-38 (LVPECL), and PL502-39
(LVDS) are high performance and low phase noise
VCXO IC chips. They provide phase noise perfor-
mance as low as –125dBc at 10kHz offset (at
155MHz), by multiplying the input crystal frequency up
to 32x. The wide pull range (±200 ppm) and very low
jitter make them ideal for a wide range of applications,
including SONET/SDH and FEC. They accept funda-
mental parallel resonant mode crystals from 12MHz to
25MHz.
BLOCK DIAGRAM
SEL[3:0]
VCON
XIN
XOUT
Oscillator
Amplifier
w/
integrated
varicaps
PLL
(Phase
Locked
Loop)
PLL by-pass
OE
CLKC
CLKT
PL502-3x
XOUT
SEL3^
SEL2^
OE
12
13
11 10
9
8
14 PL502-3x 7
15 6
16 5
123 4
GND
CLKC
VDD
CLKT
QFN-16L
OUTPUT ENABLE LOGICAL LEVELS
Part #
OE
State
PL502-38
PL502-35
PL502-37
PL502-39
0 (Default)
1
0
1 (Default)
Output enabled
Tri-state
Tri-state
Output enabled
OE input: Logical states defined by LVPECL levels for PL502-38
Logical states defined by LVCMOS levels for PL502-37/-39
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 4/15/13 Page 1
1 page  
PL502-35/-37/-38/-39
750kHz – 800MHz Low Phase Noise Multiplier VCXO
Universal Low Phase Noise ICs
5. Jitter Specifications
PARAMETERS
CONDITIONS
FREQUENCY MIN. TYP. MAX. UNITS
Period jitter RMS
With capacitive decoupling
between VDD and GND.
Over 10,000 cycles.
Period jitter
Peak-to-Peak
With capacitive decoupling
between VDD and GND.
Over 10,000 cycles.
Integrated jitter RMS Integrated 12kHz to 20MHz
19.44MHz
77.76MHz
155.52MHz
622.08MHz
19.44MHz
77.76MHz
155.52MHz
622.08MHz
155.52MHz
622.08MHz
2.2
4.5
ps
4.5
5.0
17
25
27 ps
35
2.5 4
ps
2.5 4
6. Phase Noise Specifications
PARAMETERS
FREQUENCY
19.44MHz
Phase Noise relative
to carrier (typical)
77.76MHz
155.52MHz
622.08MHz
Note: Phase Noise measured at VCON = 0V
@10Hz
-80
-72
-65
-55
@100Hz
-108
-103
-95
-85
@1kHz
-132
-122
-120
-109
@10kHz
-142
-130
-125
-115
@100kHz UNITS
-150
-125
dBc/Hz
-121
-110
7. LVCMOS Electrical Characteristics
PARAMETERS
SYMBOL
CONDITIONS
Output drive current
Output Clock Rise/Fall Time
IOH VOH= VDD-0.4V, VDD=3.3V
IOL VOL = 0.4V, VDD = 3.3V
0.3V ~ 3.0V with 15 pF load
MIN.
10
10
TYP.
2.4
MAX.
UNITS
mA
mA
ns
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 4/15/13 Page 5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet PL502-38.PDF ] | |
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