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PL520-00 の電気的特性と機能

PL520-00のメーカーはMicrelです、この部品の機能は「Low Phase Noise VCXO」です。


製品の詳細 ( Datasheet PDF )

部品番号 PL520-00
部品説明 Low Phase Noise VCXO
メーカ Micrel
ロゴ Micrel ロゴ 




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PL520-00 Datasheet, PL520-00 PDF,ピン配置, 機能
PL520-00
Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)
FE AT UR E S
100MHz to 200MHz Fundamental Mode Crystal.
Output range: 100 200MHz (no multiplication),
200 400MHz (2x multiplier), 400 700MHz (4x
multiplier), or 800MHz 1GHz (LVDS output
only for 8x multiplier).
Available outputs: PECL, LVDS, or CMOS (High
Drive (30mA) or Standard Drive (10mA) output).
Selectable OE Logic (enable high or enable low).
Integrated variable capacitors.
Supports 3.3V-Power Supply.
Available in die form.
Thickness 10 mil.
DESCRIPTION
PL520-00 is a VCXO IC specifically designed to pull
high frequency fundamental crystals. Its design was
optimized to tolerate higher limits of interelectrodes
capacitance and bonding capacitance to improve
yield. It achieves very low current into the crystal
resulting in better overall stability. Its internal
varicaps allow an on chip frequency pulling,
controlled by the VCON input.
BLOCK DIAGRAM
SEL
VCON Oscillator
Amplifier
XIN
w/
integrated
varicaps
XOUT
PLL
(Phase
Locked
Loop)
PLL by-pass
OE
Q
Q
PL520-00
DIE SPECIFICATIONS
Name
Value
Size 65 x 62 mil
Reverse side
GND
Pad dimensions
80 m icron x 80 micron
Th ic kn e s s
10 mil
DIE CONFIGURATION
65 mil
25 24 23 22 21 20 19 18
XIN 26
XOUT 27
Die ID:
A1919-19A
SEL3^ 28
SEL2^ 29
OE
30
CTRL
VCON 31
C502A
12345 6 78
(1550,1475)
17 GNDBUF
16 CMOS
15 LVDSB
14 PECLB
13 VDDBUF
12 VDDBUF
11 PECL
10 LVDS
9 OE_SEL^
Y (0,0)
X
Note: ^ denotes internal pull up
OUTPUT SELECTION AND ENABLE
OUTSEL1
(Pad #18)
0
0
1
1
OUTSEL0
(Pad #25)
0
1
0
1
Selected Output
High Drive CMOS
Standard CMOS
LVDS
PECL (default)
OE_SELECT
(Pad #9)
0
1 (Default)
OE_CTRL
(Pad #30)
0
1 (Default)
0 (Default)
1
State
Tr i- s t a te
Output enabled
Output enabled
Tr i- s t a te
Pad #9, 18, 25: Bond to GND to set to “0”. No connection results to
“default” setting through internal pull-up.
Pad #30: Logical states defined by PECL levels if OE_SELECT (pad #9)
is “1”
Logical states defined by CMOS levels if OE_SELECT is “0
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 09/20/04 Page 1

1 Page





PL520-00 pdf, ピン配列
PL520-00
Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)
3. Voltage Control Crystal Oscillator
PARAMETERS
SYMBOL
CONDITIONS
MIN. TYP. MAX. UNITS
VCXO Stabilization Time *
VCXO Tuning Range
CLK output pullability
On-chip Varicaps control range
L in e ar it y
VCXO Tuning Characteristic
VCON input impedance
VCON modulation BW
TVC XOS TB
From power valid
FXIN = 100 200MHz;
XTAL C0/C1 < 250
0V VCON 3.3V
VCON=1.65V, 1.65V
VCON = 0 to 3.3V
0V VCON 3.3V, -3dB
10 ms
200* ppm
100*
ppm
4 18*
pF
10* %
65 ppm/V
60 k
25 kHz
Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits.
4. General Electrical Specifications
PARAMETERS
Supply Current (Loaded Outputs)
Operating Voltage
Output Clock Duty Cycle
Short Circuit Current
SYMBOL
IDD
VDD
CONDITIONS
PECL/LVDS/CMOS
@ 50% VDD (CMOS)
@ 1.25V (LVDS)
@ VDD 1.3V (PECL)
MIN. TYP. MAX. UNITS
100/80/40 mA
2.97 3.63 V
45 50
45 50
45 50
55
55
55
%
50 mA
5. Jitter Specifications
PARAMETERS
Period jitter RMS
Period jitter peak-to-peak
Accumulated jitter RMS
Accumulated jitter peak-to-
peak
Random Jitter
Integrated jitter RMS at
155MHz
Period jitter RMS
Period jitter peak-to-peak
Accumulated jitter RMS
Accumulated jitter peak-to-
peak
Random Jitter
Integrated jitter RMS at
622MHz
Measured on Wavecrest SIA 3000
CONDITIONS
At 155.52MHz, with capacitive decoupling
between VDD and GND. Over 10,000 cycles
At 155.52MHz, with capacitive decoupling
between VDD and GND. Over 1,000,000
cycles.
“RJ” measured on Wavecrest SIA 3000
Integrated 12 kHz to 20 MHz
At 622.08MHz, with capacitive decoupling
between VDD and GND. Over 10,000 cycles
At 622.08MHz, with capacitive decoupling
between VDD and GND. Over 1,000,000
cycles.
“RJ” measured on Wavecrest SIA 3000
Integrated 12 kHz to 20 MHz
MIN.
TYP.
2.5
18.5
2.5
24
2.5
0.3
11
45
11
24
3
1.6
MAX.
20
27
0.4
49
27
1.8
UNITS
ps
ps
ps
ps
ps
ps
ps
ps
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 09/20/04 Page 3


3Pages


PL520-00 電子部品, 半導体
PL520-00
Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)
10. PECL Electrical Characteristics
PARAMETERS
Output High Voltage
Output Low Voltage
SYMBOL
VOH
VOL
CONDITIONS
RL = 50 to (VDD 2V)
(see figure)
11. PECL Switching Characteristics
PARAMETERS
Clock Rise Time
Clock Fall Time
SYMBOL
tr
tf
CONDITIONS
@20/80% - PECL
@80/20% - PECL
MIN.
VDD 1.025
MAX.
VDD 1.620
UNITS
V
V
MIN. TYP. MAX. UNITS
0.6 1.5
0.5 1.5
ns
ns
PECL Levels Test Circuit
OUT
VDD
502.0V
PECL Output Skew
OUT
50%
OUT
50
OUT
80%
50%
20%
OUT
tR
OUT
tSKEW
PECL Transistion Time Waveform
DUTY CYCLE
45 - 55%
55 - 45%
tF
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1(408) 944-0800 • fax +1(408) 474-1000 • www.micrel.com Rev 09/20/04 Page 6

6 Page



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部品番号部品説明メーカ
PL520-00

Low Phase Noise VCXO

Micrel
Micrel


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