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IN24AA02 の電気的特性と機能

IN24AA02のメーカーはIntegralです、この部品の機能は「2K 1.8V CMOS Serial EEPROMs」です。


製品の詳細 ( Datasheet PDF )

部品番号 IN24AA02
部品説明 2K 1.8V CMOS Serial EEPROMs
メーカ Integral
ロゴ Integral ロゴ 




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IN24AA02 Datasheet, IN24AA02 PDF,ピン配置, 機能
TECHNICAL DATA
2K 1.8V CMOS Serial EEPROMs
IN24AA02
DESCRIPTION
IN24AA02 is a 2K-bit Electrically Erasable PROM. The
device is organized as a single block of 256x8 bit
memory with a two-wire serial interface. Low voltage
design permits operation down to 1.8V with standby
and active currents of only 1μA and 3mA respectively.
The IN24AA02 also has a page-write capability for up
to 8 bytes of data.
FEATURES
Single supply with operation down to 1.8V
Two version:
o Version A – pins A0, A1, A2 are using for the
addressing on a single bus system (up to eight
ICs),
o Version B – pins A0, A1, A2 are not using. Only
one IC may be using on a bus.
Low power CMOS technology
Organized as a single block of 256 bytes (256x8)
Two wire serial interface bus, IIC compatible
Schmitt trigger, filtered inputs for noise suppression
Output slope control to eliminate ground bounce
100 kHz (1.8V) and 400 kHz (2.5-5.5V) compatibility
Self-timed write cycle (including auto-erase)
Page-write buffer for up to 8 bytes
6 ms typical write cycle time for page-write
Hardware write protect for entire memory
Can be operated as a serial ROM
Factory programming (QTP) available
ESD protection > 2,000V
1,000,000 ERASE/WRITE cycles guaranteed
Data retention > 200 years
8-pin DIP, 8-pin SOP
Temperature range -40°C to +85°C (industrial)
Package Types
PIN ASSIGNMENT
PINNING
Name
Function
VSS Ground
SDA Serial Address/Data I/O
SCL Serial Clock
WP
VCC
AO, A1, A2
Write Protect Input
+1.8V to 5.5V Power Supply
Pins for device address selection
Note: Pins A0, A1 & A2 are not used for IN24AA02B (No internal connections)
INTEGRAL

1 Page





IN24AA02 pdf, ピン配列
Figure 2. Bus timing Start/Stop
IN24AA02
AC CHARACTERISTICS
Parameter
1.8VCC<2.5V
Symbol Min Max
Clock frequency
Clock high time
Clock low time
SDA and SCL rise time
SDA and SCL fall time
FCLK
THIGH
TLOW
TR
TF
-
4000
4700
-
-
100
-
-
1000
300
START condition hold
time
THD:STA
4000
-
2.5VCC5.5V
Min Max
- 400
600 -
1300
-
- 300
- 300
600 -
START condition
setup time
Data input hold time
Data input setup time
STOP condition setup
time
Output valid from
clock
TSU:STA
THD:DAT
TSU:DAT
TSU:STO
TAA
4700 -
0
250
4000
-
-
-
- 3500
600
0
100
600
-
-
-
-
-
900
Bus free time
TBUF 4700 -
1300
-
Output fall time from
VIH min to VIL max
Input filter spike
suppres-sion (SDA &
SCL pins)
TOF
TSP
- 250 20+0.1CBB 250
- 50
-
50
Units
Remarks
kHz
ns
ns
ns Note 2
ns Note 2
ns
After this period the
first clock pulse is
generated
ns
Only relevant for
repeated START
condition
ns Note 1
ns
ns
ns Note 1
Time the bus must be
ns free before a new
transmission can start
ns CB100pF (Note2)
ns Note 3
Write cycle time
TWR
-5
-
5 ms Byte or Page mode
Note 1: As a transmitter, the device must provide an internal minimum delay time to bridge the
undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended
generation of START or STOP conditions.
Note 2: Not 100% tested. CB = total capacitance of one bus line in pF.
Note 3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs that
provide improved noise and spike suppression. This eliminates the need for a Ti
specification for standard operation.
INTEGRAL
3


3Pages


IN24AA02 電子部品, 半導体
Operation
For IN24AA02A
Read
Write
For IN24AA02B
Read
Write
Control Code
1010
1010
1010
1010
Figure 5. Control Byte Allocation
Chip Select
A2 A1 A0
A2 A1 A0
XXX
XXX
IN24AA02
R/W
1
0
1
0
A2 A1 A0
WRITE OPERATION
Byte Write
Following the start condition from the master, the device code (4 bits), the device
address selection (3 bits), and the R/W bit, which is a logic low, is placed onto the bus
by the master transmitter. This indicates to the addressed slave receiver that a byte with
a word address will follow after it has generated an acknowledge bit during the ninth
clock cycle. Therefore the next byte transmitted by the master is the word address and
will be written into the address pointer of the IN24AA02. After receiving another
acknowledge signal from the IN24AA02 the master device will transmit the data word to
be written into the addressed memory location. The IN24AA02 acknowledges again and
the master generates a stop condition. These initiates the internal write cycle, and during
this time the IN24AA02 will not generate acknowledge signals (see Figure 6).
Page Write
The write control byte, word address and the first data byte are transmitted to the
IN24AA02 in the same way as in a byte write. But instead of generating a stop condition
the master transmits up to eight data bytes to the IN24AA02, which are temporarily
stored in the on-chip page buffer and will be written into the memory after the master
has transmitted a stop condition. After the receipt of each word, the three lower order
address pointer bits are internally incremented by one. The higher order five bits of the
word address remains constant. If the master should transmit more than eight words
prior to generating the stop condition, the address counter will roll over and the previ-
ously received data will be overwritten. As with the byte write operation, once the stop
condition is received an internal write cycle will begin (see Figure 8).
INTEGRAL
6

6 Page



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部品番号部品説明メーカ
IN24AA02

2K 1.8V CMOS Serial EEPROMs

Integral
Integral


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