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25P10 の電気的特性と機能

25P10のメーカーはSTMicroelectronicsです、この部品の機能は「1 Mbit Low Voltage Paged Flash Memory」です。


製品の詳細 ( Datasheet PDF )

部品番号 25P10
部品説明 1 Mbit Low Voltage Paged Flash Memory
メーカ STMicroelectronics
ロゴ STMicroelectronics ロゴ 




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25P10 Datasheet, 25P10 PDF,ピン配置, 機能
M25P10
1 Mbit Low Voltage Paged Flash Memory
With 20 MHz Serial SPI Bus Interface
PRELIMINARY DATA
s 1 Mbit PAGED Flash Memory
s 128 BYTE PAGE PROGRAM IN 3 ms TYPICAL
s 256 Kbit SECTOR ERASE IN 1 s TYPICAL
s BULK ERASE IN 2 s TYPICAL
s SINGLE 2.7 V to 3.6 V SUPPLY VOLTAGE
s SPI BUS COMPATIBLE SERIAL INTERFACE
s 20 MHz CLOCK RATE AVAILABLE
s SUPPORTS POSITIVE CLOCK SPI MODES
s DEEP POWER DOWN MODE (1 µA TYPICAL)
s ELECTRONIC SIGNATURE
s 10,000 ERASE/PROG CYCLES PER SECTOR
s 20 YEARS DATA RETENTION
s –40 TO 85°C TEMPERATURE RANGE
DESCRIPTION
The M25P10 is an 1 Mbit Paged Flash Memory
fabricated with STMicroelectronics High
Endurance CMOS technology. The memory is
accessed by a simple SPI bus compatible serial
interface. The bus signals are a serial clock input
(C), a serial data input (D) and a serial data output
(Q).
The device connected to the bus is selected when
the chip select input (S) goes low. Data is clocked
in during the low to high transition of clock C, data
8
1
SO8 (MN)
150 mil width
8
1
SO8 (MW)
200 mil width
Figure 1. Logic Diagram
VCC
Table 1. Signal Names
C Serial Clock
D Serial Data Input
Q Serial Data Output
S Chip Select
W Write Protect
HOLD
Hold
VCC Supply Voltage
VSS Ground
D
C
S
W
HOLD
M25P10
VSS
Q
AI03744
June 2000
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/21

1 Page





25P10 pdf, ピン配列
Figure 3. Microcontroller and Memory Devices on the SPI Bus
SPI Interface with SDO
(CPOL, CPHA) = SDI
('0', '0') or ('1', '1') SCK
Master
(ST6, ST7, ST9,
ST10, Others)
CS3 CS2 CS1
CQD
M25P10
S
CQD
M25P10
S
M25P10
CQD
M25P10
S
AI03746
Once bit 7 (SRWD) of the status register has been
set to 1, the possibility to rewrite the SR depends
on the logical level present at pin W:
– If W pin is high, it will be possible to rewrite the
status register after having set the WEL (Write
Enable Latch).
– If W pin is low, any attempt to modify the status
register will be ignored by the device even if the
WEL was set. As a consequence: all the data
bytes in the memory area software protected
(SPM) by the BPi bits of the status register are
also hardware protected against data
modification and can be seen as a Read Only
memory area. This mode is called the Hardware
Protected Mode (HPM).
It is possible to enter the Hardware Protected
Mode (HPM) by setting SRWD bit after pulling
down the W pin or by pulling down the W pin after
setting SRWD bit.
The only way to abort the Hardware Protected
Mode once entered is to pull high the W pin.
If W pin is permanently tied to high level, the
Hardware Protected Mode will never be activated
and the memory will only allow the user to
software protect a part of the memory with the BPi
bits of the status register.
All protection features of the device are
summarized in Table 3.
Figure 4. Hold Condition Activation
CLOCK
HOLD PIN
MEMORY
STATUS
ACTIVE
HOLD
ACTIVE
HOLD
ACTIVE
AI02029B
3/21


3Pages


25P10 電子部品, 半導体
M25P10
Table 6. Instruction Set
Instruc
tion
Description
Instruction
Format
WREN Set Write Enable Latch
0000 0110
WRDI Reset Write Enable Latch
0000 0100
RDSR Read Status Register
0000 0101
WRSR Write Status Register
0000 0001
READ Read Data from Memory Array 0000 0011
PP
Program up to 128 Data bytes
to Memory Array
0000 0010
SE
Sector Erase (set to FFh) one
sector of Memory Array
1101 1000
BE
Bulk Erase (set to FFh) whole
of Memory Array
1100 0111
DP Enter Deep Power-down mode 1011 1001
RES
Release from Deep Power-
down mode, and Read
Electronic Signature
1010 1011
operation, a one-byte instruction code must be
sent to the chip. This code is entered via the data
input (D), and latched on the rising edge of the
clock input (C). To enter an instruction code, the
device must have been previously selected (S =
low). Table 6 shows the available instruction set.
At Power-up and Power-down, the device must
not be selected (that is the S input must follow the
voltage applied on the VCC pin) until the supply
voltage reaches the correct VCC values which are
VCC(min) at Power-up and VSS at Power-down (a
simple pull-up resistor on S insures safe and
proper power up and down phases).
Read Data Byte(s) (READ)
The device is first selected by putting S low. The
Read instruction byte is followed by a three bytes
address (A23-A0), each bit being latched-in during
the rising edge of the clock (C). Then the data
stored in the memory at the selected byte address
is shifted out on the Q output pin, each bit being
shifted out during the falling edge of the clock (C).
The first byte addressed can be any byte within a
page. The address is automatically incremented to
the next higher address after each byte of data is
shifted out. The whole memory can therefore be
read with a single Read instruction. When the
highest address is reached, the address counter
rolls over to 000000h allowing the read cycle to be
continued indefinitely.
The Read operation is terminated by deselecting
the chip. The chip can be deselected at any time
during data output. Any read attempt during an
Erase, Program or Write Status Register cycle will
be rejected and will deselect the chip without
having any effects on the ongoing operation.
The timing sequence is shown in Figure 11.
Page Program (PP)
Prior to any Page Program attempt, a write enable
instruction (WREN) must have been previously
sent (the S input driven low, WREN instruction
properly transmitted and the S input driven high).
After the WREN instruction decoding, the memory
sets the Write Enable Latch (WEL) which allows
the execution of any further Page Program
instruction. The Page Program instruction is
entered by driving the Chip select input (S) low,
followed by the instruction byte, 3 address bytes
and at least 1 data byte on Data In input (D). If the
least significant address bits differ from [A6-
A0]=000.0000, all transmitted data exceeding the
addressed page boundary will roll over and will be
programmed from address [A6-A0]=000.0000 of
this same page. The Chip Select input (S) must be
driven low for the entire duration of the sequence.
Figure 7. WREN: Set Write Enable Latch Sequence
S
01234567
C
INSTRUCTION
D
HIGH IMPEDANCE
Q
AI02281B
6/21

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