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PDF IRF840S Data sheet ( Hoja de datos )

Número de pieza IRF840S
Descripción Power MOSFET ( Transistor )
Fabricantes Vishay 
Logotipo Vishay Logotipo



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No Preview Available ! IRF840S Hoja de datos, Descripción, Manual

Power MOSFET
IRF840S, SiHF840S
Vishay Siliconix
PRODUCT SUMMARY
VDS (V)
RDS(on) ()
Qg (Max.) (nC)
Qgs (nC)
Qgd (nC)
Configuration
500
VGS = 10 V
63
9.3
32
Single
0.85
D2PAK (TO-263)
D
GD
S
G
S
N-Channel MOSFET
ORDERING INFORMATION
Package
D2PAK (TO-263)
Lead (Pb)-free and Halogen-free
SiHF840S-GE3
Lead (Pb)-free
IRF840SPbF
SiHF840S-E3
Note
a. See device orientation.
FEATURES
Halogen-free According to IEC 61249-2-21
Definition
• Surface Mount
• Available in Tape and Reel
• Dynamic dV/dt Rating
• Repetitive Avalanche Rated
• Fast Switching
• Ease of Paralleling
• Simple Drive Requirement
• Compliant to RoHS Directive 2002/95/EC
DESCRIPTION
Third generation Power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.
The D2PAK (TO-263) is a surface mount power package
capable of accommodating die size up to HEX-4. It provides
the highest power capability and the lowest possible
on-resistance in any existing surface mount package. The
D2PAK (TO-263) is suitable for high current applications
because of its low internal connection resistance and can
dissipate up to 2.0 W in a typical surface mount application.
D2PAK (TO-263)
SiHF840STRL-GE3a
IRF840STRLPbFa
SiHF840STL-E3a
D2PAK (TO-263)
SiHF840STRR-GE3a
IRF840STRRPbFa
SiHF840STR-E3a
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
Pulsed Drain Currenta
VGS at 10 V
TC = 25 °C
TC = 100 °C
Linear Derating Factor
Linear Derating Factor (PCB Mount)e
Single Pulse Avalanche Energyb
Avalanche Currenta
Repetiitive Avalanche Energya
Maximum Power Dissipation
Maximum Power Dissipation (PCB Mount)e
Peak Diode Recovery dV/dtc
TC = 25 °C
TA = 25 °C
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
for 10 s
VDS
VGS
ID
IDM
EAS
IAR
EAR
PD
dV/dt
TJ, Tstg
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = 50 V, starting TJ = 25 °C, L = 14 mH, Rg = 25 , IAS = 8.0 A (see fig. 12).
c. ISD 8.0 A, dI/dt 100 A/μs, VDD VDS, TJ 150 °C.
d. 1.6 mm from case.
e. When mounted on 1" square PCB (FR-4 or G-10 material).
LIMIT
500
± 20
8.0
5.1
32
1.0
0.025
510
8.0
13
125
3.1
3.5
- 55 to + 150
300d
UNIT
V
A
W/°C
mJ
A
mJ
W
V/ns
°C
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 91071
S11-1050-Rev. C, 30-May-11
www.vishay.com
1
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

1 page




IRF840S pdf
8.0
6.0
4.0
2.0
0.0
25
91071_09
50 75 100 125
TC, Case Temperature (°C)
150
Fig. 9 - Maximum Drain Current vs. Case Temperature
IRF840S, SiHF840S
Vishay Siliconix
VDS
VGS
Rg
RD
D.U.T.
10 V
Pulse width 1 µs
Duty factor 0.1 %
+- VDD
Fig. 10a - Switching Time Test Circuit
VDS
90 %
10 %
VGS
td(on) tr
td(off) tf
Fig. 10b - Switching Time Waveforms
10
1
D = 0.5
0.2
0.1 0.1
0.05
0.02
0.01
10-2
10-3
10-5
91071_11
Single Pulse
(Thermal Response)
10-4
10-3
10-2
0.1
t1, Rectangular Pulse Duration (s)
PDM
t1
t2
Notes:
1. Duty Factor, D = t1/t2
2. Peak Tj = PDM x ZthJC + TC
1 10 102
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
Document Number: 91071
S11-1050-Rev. C, 30-May-11
www.vishay.com
5
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

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