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IRF614SのメーカーはVishayです、この部品の機能は「Power MOSFET ( Transistor )」です。 |
部品番号 | IRF614S |
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部品説明 | Power MOSFET ( Transistor ) | ||
メーカ | Vishay | ||
ロゴ | |||
このページの下部にプレビューとIRF614Sダウンロード(pdfファイル)リンクがあります。 Total 9 pages
Power MOSFET
IRF614S, SiHF614S
Vishay Siliconix
PRODUCT SUMMARY
VDS (V)
RDS(on) ()
Qg (Max.) (nC)
Qgs (nC)
Qgd (nC)
Configuration
250
VGS = 10 V
8.2
1.8
4.5
Single
D2PAK (TO-263)
D
2.0
GD
S
G
S
N-Channel MOSFET
ORDERING INFORMATION
Package
Lead (Pb)-free and Halogen-free
Lead (Pb)-free
Note
a. See device orientation.
D2PAK (TO-263)
SiHF614S-GE3
IRF614SPbF
SiHF614S-E3
FEATURES
• Halogen-free According to IEC 61249-2-21
Definition
• Surface Mount
• Available in Tape and Reel
• Dynamic dV/dt Rating
• Repetitive Avalanche Rated
• Fast Switching
• Ease of Paralleling
• Simple Drive Requirements
• Compliant to RoHS Directive 2002/95/EC
DESCRIPTION
Third generation Power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.
The D2PAK (TO-263) is a surface mount power package
capable of accommodating die sizes up to HEX-4. It
provides the highest power capability and the lowest
possible on-resistance in any existing surface mount
package. The D2PAK (TO-263) is suitable for high current
applications because of its low internal connection
resistance and can dissipate up to 2.0 W in a typical surface
mount application.
D2PAK (TO-263)
-
IRF614STRLPbFa
SiHF614STL-E3a
D2PAK (TO-263)
SiHF614STRR-GE3a
IRF614STRRPbFa
SiHF614STR-E3a
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
Pulsed Drain Currenta
Linear Derating Factor
Linear Derating Factor (PCB Mount)e
Single Pulse Avalanche Energyb
Avalanche Currenta
Repetitive Avalanche Energya
Maximum Power Dissipation
Maximum Power Dissipation (PCB Mount)e
Peak Diode Recovery dV/dtc
VGS at 10 V
TC = 25 °C
TC = 100 °C
VDS
VGS
ID
IDM
TC = 25 °C
TA = 25 °C
EAS
IAR
EAR
PD
dV/dt
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
for 10 s
TJ, Tstg
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = 50 V, starting TJ = 25 °C, L = 13 mH, Rg = 25 , IAS = 2.7 A (see fig. 12).
c. ISD 2.7 A, dI/dt 65 A/μs, VDD VDS, TJ 150 °C.
d. 1.6 mm from case.
e. When mounted on 1" square PCB (FR-4 or G-10 material).
LIMIT
250
± 20
2.7
1.7
8.0
0.29
0.025
61
2.7
3.6
36
3.1
4.8
- 55 to + 150
300d
UNIT
V
A
W/°C
mJ
A
mJ
W
V/ns
°C
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 91026
S11-1063-Rev. C, 30-May-11
www.vishay.com
1
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
1 Page TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
IRF614S, SiHF614S
Vishay Siliconix
VGS
Top 15 V
10 V
8.0 V
7.0 V
100 6.0 V
5.5 V
5.0 V
Bottom 4.5 V
10-1
4.5 V
10-2
10-1
91026_01
20 µs Pulse Width
TC = 25 °C
100 101
VDS, Drain-to-Source Voltage (V)
Fig. 1 - Typical Output Characteristics, TC = 25 °C
100 150 °C
25 °C
10-1
10-2
91026_03
4
20 µs Pulse Width
VDS = 50 V
5 6 7 8 9 10
VGS, Gate-to-Source Voltage (V)
Fig. 3 - Typical Transfer Characteristics
VGS
Top 15 V
10 V
8.0 V
100 7.0 V
6.0 V
5.5 V
5.0 V
Bottom 4.5 V
10-1
4.5 V
10-2
10-1
91026_02
20 µs Pulse Width
TC = 150 °C
100 101
VDS, Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics, TC = 150 °C
3.0 ID = 2.7 A
VGS = 10 V
2.5
2.0
1.5
1.0
0.5
0.0
- 60 - 40 - 20 0 20 40 60 80 100 120 140 160
91026_04
TJ, Junction Temperature (°C)
Fig. 4 - Normalized On-Resistance vs. Temperature
Document Number: 91026
S11-1063-Rev. C, 30-May-11
www.vishay.com
3
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
3Pages IRF614S, SiHF614S
Vishay Siliconix
VDS
Vary tp to obtain
required IAS
Rg
10 V
tp
L
D.U.T
IAS
0.01 Ω
+
- V DD
Fig. 12a - Unclamped Inductive Test Circuit
VDS
VDS
tp
VDD
IAS
Fig. 12b - Unclamped Inductive Waveforms
140
ID
120 Top 1.2 A
1.7 A
100 Bottom 2.7 A
80
60
40
20
VDD = 50 V
0
25 50
75 100 125 150
91026_12c
Starting TJ, Junction Temperature (°C)
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
10 V
QGS
VG
QG
QGD
Charge
Fig. 13a - Basic Gate Charge Waveform
Current regulator
Same type as D.U.T.
12 V
50 kΩ
0.2 µF
0.3 µF
+
D.U.T. - VDS
VGS
3 mA
IG ID
Current sampling resistors
Fig. 13b - Gate Charge Test Circuit
www.vishay.com
6
Document Number: 91026
S11-1063-Rev. C, 30-May-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
6 Page | |||
ページ | 合計 : 9 ページ | ||
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