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PDF 74HCT2G126DC Data sheet ( 特性 )

部品番号 74HCT2G126DC
部品説明 Dual buffer/line driver
メーカ NXP Semiconductors
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74HCT2G126DC Datasheet, 74HCT2G126DC PDF,ピン配置, 機能
74HC2G126; 74HCT2G126
Dual buffer/line driver; 3-state
Rev. 5 — 18 December 2013
Product data sheet
1. General description
The 74HC2G126; 74HCT2G126 is a dual buffer/line driver with 3-state outputs controlled
by the output enable inputs (nOE). Inputs include clamp diodes. This enables the use of
current limiting resistors to interface inputs to voltages in excess of VCC.
2. Features and benefits
Wide operating voltage from 2.0 V to 6.0 V
Input levels:
For 74HC2G126: CMOS level
For 74HCT2G126: TTL level
Complies with JEDEC standard no. 7A
Symmetrical output impedance
High noise immunity
Low power dissipation
Balanced propagation delays
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74HC2G126DP 40 C to +125 C TSSOP8
74HCT2G126DP
74HC2G126DC 40 C to +125 C VSSOP8
74HCT2G126DC
74HC2G126GD 40 C to +125 C XSON8
74HCT2G126GD
Description
plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
Version
SOT505-2
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
plastic extremely thin small outline package; no leads; SOT996-2
8 terminals; body 3 2 0.5 mm

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74HCT2G126DC pdf, ピン配列
NXP Semiconductors
74HC2G126; 74HCT2G126
Dual buffer/line driver; 3-state
6.2 Pin description
Table 3. Pin description
Symbol
Pin
1OE, 2OE
1, 7
1A, 2A
2, 5
1Y, 2Y
6, 3
GND
4
VCC
8
Description
output enable input
data input
data output
ground (0 V)
supply voltage
7. Functional description
Table 4.
Input
nOE
H
H
L
Function table[1]
nA
L
H
X
Output
nY
L
H
Z
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min Max Unit
VCC
IIK
IOK
IO
ICC
IGND
Tstg
Ptot
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
VO = 0.5 V to (VCC + 0.5 V)
0.5
[1] -
[1] -
[1] -
-
70
65
[2] -
+7.0
20
20
35
70
-
+150
300
V
mA
mA
mA
mA
mA
C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For TSSOP8 package: above 55 C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110 C the value of Ptot derates linearly with 8 mW/K.
For XSON8 package: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
74HC_HCT2G126
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 18 December 2013
© NXP B.V. 2013. All rights reserved.
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3Pages


74HCT2G126DC 電子部品, 半導体
NXP Semiconductors
74HC2G126; 74HCT2G126
Dual buffer/line driver; 3-state
Table 8. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 8.
Symbol Parameter Conditions
Tamb = 40 C to +85 C Tamb = 40 C to +125 C Unit
Min Typ[1] Max
Min
Max
ten enable time nOE to nY; see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
tdis disable time nOE to nY; see Figure 7
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
tt transition nY; see Figure 6
time
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
CPD power
per buffer; VI = GND to VCC
dissipation
capacitance
output enabled
output disabled
[2]
-
-
-
[2]
-
-
-
[2]
-
-
-
[3]
-
-
40 115
11 23
8 20
25 125
12 25
10 21
18 75
6 15
5 13
11 -
1-
-
-
-
-
-
-
-
-
-
-
-
135 ns
27 ns
23 ns
150 ns
30 ns
26 ns
90 ns
18 ns
15 ns
- pF
- pF
74HCT2G126
tpd propagation nA to nY; see Figure 6
delay
VCC = 4.5 V
[2]
-
15 30
VCC = 5.0 V; CL = 15 pF
- 12 -
ten enable time nOE to nY; see Figure 7;
VCC = 4.5 V
[2] -
11 31
tdis disable time nOE to nY; see Figure 7;
VCC = 4.5 V
[2] -
11 35
tt
transition nY; see Figure 6; VCC = 4.5 V
[2] -
6 15
time
-
-
-
-
-
36 ns
- ns
38 ns
42 ns
18 ns
CPD power
per buffer;
dissipation VI = GND to VCC 1.5 V
capacitance output enabled
[3]
- 11 -
-
- pF
output disabled
-1 -
-
- pF
[1] All typical values are measured at Tamb = 25 C.
[2] tpd is the same as tPLH and tPHL.
ten is the same as tPZL and tPZH.
tdis is the same as tPLZ and tPHZ.
tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
74HC_HCT2G126
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 18 December 2013
© NXP B.V. 2013. All rights reserved.
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