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HY628400LLG の電気的特性と機能

HY628400LLGのメーカーはHynix Semiconductorです、この部品の機能は「512K x 8bit CMOS SRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 HY628400LLG
部品説明 512K x 8bit CMOS SRAM
メーカ Hynix Semiconductor
ロゴ Hynix Semiconductor ロゴ 




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HY628400LLG Datasheet, HY628400LLG PDF,ピン配置, 機能
HY628400 Series
512Kx8bit CMOS SRAM
DESCRIPTION
The HY628400 is a high-speed, low power and
4M bits CMOS SRAM organized as 524,288
words by 8 bits. The HY628400 uses Hyundai's
high performance twin tub CMOS process
technology and was designed for high-speed and
low power circuit technology. It is particulary well
suited for use in high-density and low power
system applications. This device has a data
retention mode that guarantees data to remain
valid at the minimum power supply voltage of
2.0V.
Product
Voltage Speed Operation
No. (V) (ns) Current(mA)
HY628400
5.0 55/70/85
10
Note 1. Normal : Normal Temperature
2. Current value are max.
FEATURES
Fully static operation and Tri-state outputs
TTL compatible inputs and outputs
Low power consumption
Battery backup(L/LL-part)
- 2.0V(min) data retention
Standard pin configuration
- 32pin 525mil SOP
- 32pin 400mil TSOP-II
(Standard and Reversed)
Standby Current(uA)
L LL
100 30
Temperature
(°C)
0~70(Normal)
PIN CONNECTION
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SOP
32 Vcc A18 1
31
30
29
A15
A17
/WE
A16
A14
A12
2
3
4
28 A13
A7 5
27 A8
A6 6
26
25
A9
A11
24 /OE
A5 7
A4 8
A3 9
23
22
21
20
A10
/CS
I/O8
I/O7
A2
A1
A0
I/O1
10
11
12
13
19 I/O6 I/O2 14
18
17
I/O5 I/O3
I/O4 Vss
15
16
32 Vcc Vcc 32
31 A15 A15 31
30 A17 A17 30
29 /WE /WE 29
28 A13 A13 28
27 A8
A8 27
26
25
24
A9
A11
/OE
A9
A11
/OE
26
25
24
23
22
A10
/CS
A10
/CS
23
22
21
20
I/O8 I/O8
I/O7 I/O7
21
20
19 I/O6 I/O6 19
18 I/O5 I/O5 18
17 I/O4 I/O4 17
1
2
3
4
A18
A16
A14
A12
5 A7
6
7
A6
A5
8 A4
9 A3
10 A2
11
12
A1
A0
13 I/O1
14 I/O2
15 I/O3
16 Vss
TSOP-II(Standard)
TSOP-II(Reversed)
PIN DESCRIPTION
Pin Name
/CS
/WE
/OE
A0 ~ A18
I/O1 ~ I/O8
Vcc
Vss
Pin Function
Chip Select
Write Enable
Output Enable
Address Input
Data Input/Output
Power(5.0V)
Ground
BLOCK DIAGRAM
A0 ROW DECODER
A18
/CS
/OE
/WE
MEMORY ARRAY
1024x4096
I/O1
I/O8
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.04 /Jan.99
Hyundai Semiconductor

1 Page





HY628400LLG pdf, ピン配列
HY628400 Series
DC ELECTRICAL CHARACTERISTICS
Vcc = 5.0V ±10%, TA = 0°C to 70°C (Normal) unless otherwise specified
Symbol
Parameter
Test Condition
ILI Input Leakage Current
Vss < VIN < Vcc
ILO Output Leakage Current
Vss < VOUT < Vcc, /CS = VIH or
or /OE = VIH or /WE = VIL
Icc Operating Power Supply
/CS = VIL,
Current
VIN = VIH or VIL, II/O = 0mA
ICC1 Average Operating Current
/CS = VIL
Min Duty Cycle = 100%, II/O =
0mA
ISB TTL Standby Current
/CS = VIH
(TTL Input)
ISB1 Standby Current HY628400 /CS > Vcc - 0.2V
L
(CMOS Input)
LL
VOL Output Low Voltage
IOL = 2.1mA
VOH Output High Voltage
IOH = -1mA
Min Typ Max Unit
...
-1 -
1 uA
-1 -
1 uA
- 5 10 mA
- 50 80 mA
- 0.4 2 mA
- - 100 uA
- - 30 uA
- - 0.4 V
2.4 - - V
Note : Typical values are at Vcc = 5.0V, TA = 25°C
ERISTICS
Vcc = 5.0V ± 10%, TA = 0°C to 70°C (Normal) unless otherwise specified
# Symbol
Parameter
-55 -70
Min. Max. Min. Max.
READ CYCLE
1 Trc
Read Cycle Time
55 - 70 -
2 TAA Address Access Time
- 55 - 70
3 TACS Chip Select Access Time
- 55 - 70
4 TOE Output Enable to Output Valid
- 25 - 35
5 TCLZ Chip Select to Output in Low Z
10 - 10 -
6 TOLZ Output Enable to Output in Low Z
5-5-
7 TCHZ Chip Deselection to Output in High Z
0 20 0 25
8 TOHZ Out Disable to Output in High Z
0 20 0 25
9 tOH Output Hold from Address Change
10 - 10 -
WRITE CYCLE
10 tWC Write Cycle Time
55 - 70 -
11 tCW Chip Selection to End of Write
45 - 60 -
12 tAW Address Valid to End of Write
45 - 60 -
13 tAS
Address Set-up Time
0-0-
14 tWP Write Pulse Width
40 - 50 -
15 tWR Write Recovery Time
0-0-
16 tWHZ Write to Output in High Z
0 20 0 25
17 tDW Data to Write Time Overlap
25 - 30 -
18 tDH Data Hold from Write Time
0-0-
19 tOW Output Active from End of Write
5-5-
-85
Min Max.
85 -
- 85
- 85
- 45
10 -
5-
0 30
0 30
10 -
85 -
70 -
70 -
0-
55 -
0-
0 30
35 -
0-
5-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev.04/Jan99
3


3Pages


HY628400LLG 電子部品, 半導体
WRITE CYCLE 1(/OE Clocked)
ADDR
tWC
HY628400 Series
OE
tAW
tCW
CS
tAS tWP tWR
WE
Data In
Data
Out
tOHZ
tDW
tDH
Data Valid
WRITE CYCLE 2 (/OE Low Fixed)
ADDR
CS
tAS
WE
tWC
tAW
tCW
tWP
tWR
Data In
Data
Out
tWHZ
tDW
tDH
Data Valid
tOW
(7) (8)
Notes(WRITE CYCLE):
1. A write occurs during the overlap of a low /CS and low /WE. A write begins at the latest transition among
/CS going low /WE going low: A write end at the earliest transition among /CS going high and /WE going
high. tWP is measured from the beginning of write to the end of write. .
2. tCW is measured from the later of /CS going low to the end of write .
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change.
5. If /OE and /WE are in the read mode during this period, and the I/O pins are in the output low-Z state.
Inputs of opposite phase of the output must not be applied because bus contention can occur.
6. If /CS goes low simultaneously with /WE going low, the outputs remain in high impedance state.
7. Dout is the read data of the new address.
8. When /CS is low, I/O pins are in the output state. The input signals in the opposite phase
leading to the outputs should not be applied.
Rev.04/Jan99
6

6 Page



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