|
|
PDF ST7294 Data sheet ( Hoja de datos )
| Número de pieza | ST7294 | |
| Descripción | 8-BIT MCU | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ST7294 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
ST7294
8-BIT MCU WITH 6K ROM, EEPROM AND 16-BIT TIMER WITH
INPUT CAPTURE AND DUAL OUTPUT COMPARE
n 2.5 to 5.5V Supply Operating Range
n 4MHz Maximum Clock Frequency
n Fully Static operation
n -40° to +85°C Operating Temperature Range
n Run, Wait, Stop and RAM Retention modes
n User ROM: 6,144 bytes
n Data RAM: 224 bytes
n EEPROM: 256 bytes
n 28 pin Dual-in-Line and SO plastic packages
n 22 Bidirectional I/O lines
n 6 Interrupt Wake-Up programmable input lines
n 16-bit Timer with Input Capture and dual
Output Compare
n 2V RAM Data Retention mode
n Master Reset and Power-On Reset
n Maskable Options for:
– Input Capture (ICAP) and Output Compare
(OCMP) signal pinouts
– PORT C Wake-Up function
– PORT A Open-Drain outputs
– PORTS A and B input Pull-Ups
– Watchdog Enabled/Disabled following Reset
– Watchdog Enabled during WAIT mode
n 8-bit Data Manipulation
n 63 Basic Instructions
n 17 main Addressing Modes
n 8x8 Unsigned Multiply instruction
n True Bit Manipulation
n Complete Development Support on PC/DOS
Real-Time Emulator
n Full Software Package (Cross-Assembler,
Debugger)
n Full Hardware Emulator
n EPROM and OTP support
PDIP28
PSO28
(See end of Datasheet for Ordering Information)
Figure 1. Pin Description
(1)
INT
RESET
OSCin
OSCout
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PC5
PC4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VSS
27 VDD
26 PA0
25 PA1
24 PA2
23 PA3
22 PA4
21 PA5
20 PA6
19 PA7
18 PC0 (ICAP)
17 PC1 (OCMP1)
16 PC2
15 PC3
VR0A1734
September 1995
1/69
1 page  
ST7294
1.2 PIN DESCRIPTION
VDD Power supply.
VSS Ground.
OSCin, OSCout Oscillator input and output
pins. These pins are usually connected to a paral-
lel resonant crystal or ceramic resonator. An ex-
ternal clock source may also be input via OSCin.
RESET An active-low input signal on this pin
forces initialisation of the MCU. This is the highest
priority interrupt and it is not maskable. This pin is
set to an output-low level following release on the
part of the Watchdog. The pin may be used to re-
set external peripherals.
INT This is the external interrupt input, which may
be software-configured in one of four triggering
modes.
Caution: The INT pin is also used to select an in-
ternal non-user test mode reserved exclusively for
use by SGS-THOMSON Microelectronics. This
non-user mode is entered on the rising edge of the
Reset signal, if:
– the voltage applied to the INT pin is less than
VDD + 0.5V, the device will initialise correctly in
User mode;
– if a “high” voltage (typically > VDD + 3V, @ VDD
= +5V) is applied to the pin, the device will start
in a reserved non-user mode.
Under certain operating conditions apparent de-
vice malfunction may be experienced: this may be
described as follows:
During the Reset phase, if the VDD supply risetime
is slow, the Reset rising edge may occur at a volt-
age level lower than the minimum allowed voltage
of 2.5V. In this case, the “high” voltage which
needs to be applied to the INT pin to enter the spe-
cial mode may be as low as 3.5V, and such a volt-
age level may be supplied by the external interrupt
source, thus provoking an apparent system mal-
function.
For this reason it is strongly recommended to
manage the INT pin, either by tying it to VDD, if
unused, or by connecting it to VDD via a diode, if it
is to be used: this will avoid unexpected entry into
non-user mode.
ICAP (PC0). Input Capture signal directed to the
TIMER system. This pin, according to the chosen
mask option, may be defined as the ICAP function
input, or as a standard PC0 pin. When the pin is
defined as the ICAP input, the internal pull-up re-
sistor is not connected.
OCMP1 (PC1). Output Compare signal originating
from the TIMER system. This pin may, depending
on the chosen mask option, be defined as the
OCMP1 function output (Output Compare 1 of the
Timer) or as a standard PC1 pin. When the pin is
defined as OCMP1, the internal pull-up resistor is
not connected.
PA0-PA7, PB0-PB7, PC0-PC5. These 22 lines
are standard I/O lines, programmable as either in-
puts or outputs.
– PORT A 8 standard I/O lines, bit-programma-
ble via the DDRA and DRA registers. Depending
on the chosen mask option, the outputs may be
defined as standard push-pull or as open-drain.
A further mask option allows a resistor to be add-
ed on each line when it is defined as an input.
– PORT B 8 standard I/O lines bit-programmable
via the DDRB and DRB registers. A mask option
allows a resistor to be added on each line when
it is defined as an input.
– PORT C 6 standard I/O lines bit-programma-
ble via the DDRC and DRC registers. Depending
on the chosen mask option, these 6 lines can be
defined as 6 falling-edge-sensitive interrupt lines,
linked to a single interrupt vector, or as 6 stand-
ard input ports tied to VDD through an internal pull-
up resistor. These negative edge sensitive inter-
rupt lines are capable of waking-up the ST7294
from WAIT or HALT mode. This feature allows
one to build low power applications where the
ST7294 can be woken-up by a key being
pressed.
5/69
5 Page 
ST7294
CLOCK SYSTEM (Continued)
3.1.3 Ceramic Resonator
A ceramic resonator may be used in place of the
crystal in low cost applications. The circuit on Fig-
ure 8 is recommended when using a ceramic res-
onator. The table lists the recommended capaci-
tance and feedback resistance values. The manu-
facturer of the particular ceramic resonator being
considered should be consulted for specific infor-
mation.
3.1.4 External Clock
An external clock should be applied to the OSCin
input with the OSCout pin not connected, as
shown on Figure 6. The tOXOV and tILCH specifica-
tions do not apply when using an external clock in-
put. The equivalent specification of the external
clock source should be used instead of tOXOV or
tILCH.
Table 2. Recommended Settings for Crystal
RSMAX
C0
C1
COSCin
COSCout
RP
Q
2MHz
400
5
8
15-40
15-30
10
30
4MHz
75
7
12
15-30
15-25
10
40
Unit
W
pF
nF
pF
pF
MΩ
103
Table 3. Recommended Settings for Ceramic
Resonator
RSMAX
C0
C1
COSCin
COSCout
RP
Q
2-4MHz
10
40
4.3
30
30
1-10
1250
Unit
W
pF
nF
pF
pF
MΩ
3.2 MISCELLANEOUS REGISTER
Miscellaneous Register (000Ch)
Register Address: 08h — Read/Write
Reset Value: 0001 000 (10h)
This is a miscellaneous 8-bit register, of which
only 4 bits are used for interrupt, slow mode and
Watchdog purposes.
70
- INTP INTN - - - SM WDOG
b7, b4-b2 = Unused
b6 = INTP: External Interrupt Positive allows se-
lection of the INT line triggering mode in conjunc-
tion with INTN. It can only be modified when the I
bit of the CC Register is set.
b5 = ININ: External Interrupt Negative allows se-
lection the INT line triggering mode in conjunction
with INTP. It can only be modified when the I bit of
the CC Register is set.
b1 = SM: Slow Mode. Setting this bit to 1 enables
Slow Mode, thus reducing power consumption. In
this mode, an extra divide-by-16 is added in the
clock circuitry.
b0 = WDOG: Watchdog System. Whatever the
WATCHDOG ENABLE MODE mask option, the
watchdog counter is reset when WDOG is set to 1.
When the MCU is configured with the “program-
mable enable” option, the WDOG bit is low follow-
ing a reset. The bit must be set to enable the
watchdog system. Only a reset can clear WDOG.
11/69
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ST7294.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ST7294 | 8-BIT MCU | STMicroelectronics |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |