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5821 の電気的特性と機能

5821のメーカーはAllegro MicroSystemsです、この部品の機能は「BiMOS II 8-Bit Serial Input Latched Driver」です。


製品の詳細 ( Datasheet PDF )

部品番号 5821
部品説明 BiMOS II 8-Bit Serial Input Latched Driver
メーカ Allegro MicroSystems
ロゴ Allegro MicroSystems ロゴ 




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5821 Datasheet, 5821 PDF,ピン配置, 機能
A5821
BiMOS II 8-Bit Serial Input Latched Driver
Discontinued Product
These parts are no longer in production The device should not be
purchased for new design applications. Samples are no longer available.
Date of status change: October 31, 2005
Recommended Substitutions:
For new customers or new applications, refer to the A6821.
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan for a
product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The information
included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor
for any infringements of patents or other rights of third parties which may result from its use.

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5821 pdf, ピン配列
5821
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
TYPICAL INPUT CIRCUITS
VDD
IN
STROBE &
OUTPUT
ENABLE
CLOCK &
SERIAL
DATA IN
IN
Dwg. EP-010-3
VDD
Dwg. EP-010-4A
FUNCTIONAL BLOCK DIAGRAM
CLOCK 1
SERIAL
DATA IN
2
LOGIC
GROUND 3
SERIAL-PARALLEL SHIFT REGISTER
LATCHES
VDD
4 LOGIC
SUPPLY
5
SERIAL
DATA OUT
6 STROBE
7
OUTPUT ENABLE
(ACTIVE LOW)
MOS
BIPOLAR
16 15 14
13 12
11 10
9
OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 OUT 8
SUB
POWER
8 GROUND
Dwg. FP-013A
NOTE — There is an indeterminate resistance between logic ground and power
ground. For proper operation, these terminals must be externally connected
together.
Number of Outputs ON UCN5821A Max. Allowable Duty Cycle
(IOUT = 200 mA
VDD = 12 V)
at Ambient Temperature of
25°C 40°C 50°C 60°C 70°C
8 90% 79% 72% 65% 57%
7 100% 90% 82% 74% 65%
6 100% 100% 96% 86% 76%
5 100% 100% 100% 100% 91%
4 100% 100% 100% 100% 100%
3 100% 100% 100% 100% 100%
2 100% 100% 100% 100% 100%
1 100% 100% 100% 100% 100%
TYPICAL OUTPUT DRIVER
OUT
7.2K
3K
SUB
Dwg. No. A-14,314
Number of Outputs ON UCN5821LW Max. Allowable Duty Cycle
(IOUT = 200 mA
VDD = 12 V)
at Ambient Temperature of
25°C 40°C 50°C 60°C 70°C
8 67% 59% 54% 49% 43%
7 77% 68% 62% 56% 49%
6 90% 79% 72% 65% 57%
5 100% 95% 86% 78% 68%
4 100% 100% 100% 98% 86%
3 100% 100% 100% 100% 100%
2 100% 100% 100% 100% 100%
1 100% 100% 100% 100% 100%
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 1985, 2004 Allegro MicroSystems, Inc.


3Pages


5821 電子部品, 半導体
5821
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
16
0.280
0.240
UCN5821A
Dimensions in Inches
(controlling dimensions)
9
0.014
0.008
0.430
MAX
0.300
BSC
1
0.070
0.045
0.210
MAX
0.015
MIN
0.022
0.014
16
7.11
6.10
0.775
0.735
0.100
BSC
8
0.005
MIN
0.150
0.115
Dimensions in Millimeters
(for reference only)
9
Dwg. MA-001-16A in
0.355
0.204
10.92
MAX
7.62
BSC
1
1.77
1.15
5.33
MAX
19.68
18.67
2.54
BSC
8
0.13
MIN
0.39
MIN
0.558
0.356
NOTES: 1. Lead thickness is measured at seating plane or below.
2. Lead spacing tolerance is non-cumulative.
3. Exact body and lead configuration at vendor’s option within limits shown.
3.81
2.93
Dwg. MA-001-16A mm
www.allegromicro.com

6 Page



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共有リンク

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部品番号部品説明メーカ
5821

BiMOS II 8-Bit Serial Input Latched Driver

Allegro MicroSystems
Allegro MicroSystems
5822

BiMOS II 8-Bit Serial Input Latched Driver

Allegro MicroSystems
Allegro MicroSystems


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