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54ACT715 の電気的特性と機能

54ACT715のメーカーはNational Semiconductorです、この部品の機能は「Programmable Video Sync Generator」です。


製品の詳細 ( Datasheet PDF )

部品番号 54ACT715
部品説明 Programmable Video Sync Generator
メーカ National Semiconductor
ロゴ National Semiconductor ロゴ 




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54ACT715 Datasheet, 54ACT715 PDF,ピン配置, 機能
December 1998
LM188254ACT715
LM1882-R54ACT715-R Programmable Video Sync
Generator
General Description
The ’ACT715/LM1882 and ’ACT715-R/LM1882-R are 20-pin
TTL-input compatible devices capable of generating Hori-
zontal, Vertical and Composite Sync and Blank signals for
televisions and monitors. All pulse widths are completely de-
finable by the user. The devices are capable of generating
signals for both interlaced and noninterlaced modes of op-
eration. Equalization and serration pulses can be introduced
into the Composite Sync signal when needed.
Four additional signals can also be made available when
Composite Sync or Blank are used. These signals can be
used to generate horizontal or vertical gating pulses, cursor
position or vertical Interrupt signal.
These devices make no assumptions concerning the system
architecture. Line rate and field/frame rate are all a function
of the values programmed into the data registers, the status
register, and the input clock frequency.
The ’ACT715/LM1882 is mask programmed to default to a
Clock Disable state. Bit 10 of the Status Register, Register 0,
defaults to a logic “0”. This facilitates (re)programming be-
fore operation.
The ’ACT715-R/LM1882-R is the same as the ’ACT715/
LM1882 in all respects except that the ’ACT715-R/
LM1882-R is mask programmed to default to a Clock En-
abled state. Bit 10 of the Status Register defaults to a logic
“1”. Although completely (re)programmable, the ’ACT715-R/
LM1882-R version is better suited for applications using the
default 14.31818 MHz RS-170 register values. This feature
allows power-up directly into operation, following a single
CLEAR pulse.
Features
n Maximum Input Clock Frequency > 130 MHz
n Interlaced and non-interlaced formats available
n Separate or composite horizontal and vertical Sync and
Blank signals available
n Complete control of pulse width via register
programming
n All inputs are TTL compatible
n 8 mA drive on all outputs
n Default RS170/NTSC values mask programmed into
registers
n 4 KV minimum ESD immunity
n ’ACT715-R/LM1882-R is mask programmed to default to
a Clock Enable state for easier start-up into
14.31818 MHz RS170 timing
Connection Diagrams
Pin Assignment for
DIP and SOIC
Pin Assignment
for LCC
DS100232-1
Order Number LM1882CN or LM1882CM
For Default RS-170, Order Number
LM1882-RCN or LM1882-RCM
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
FACTis a trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100232
DS100232-2
www.national.com

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54ACT715 pdf, ピン配列
Register Description (Continued)
Bits 0–2
B2 B1 B0
000
(DEFAULT)
001
010
011
100
101
110
111
VCBLANK
CBLANK
VBLANK
CBLANK
VBLANK
CBLANK
VBLANK
CBLANK
VBLANK
VCSYNC HBLHDR HSYNVDR
CSYNC HGATE VGATE
CSYNC
VSYNC
VSYNC
CSYNC
CSYNC
VSYNC
VSYNC
HBLANK
HGATE
HBLANK
CURSOR
HBLANK
CURSOR
HBLANK
VGATE
HSYNC
HSYNC
VINT
VINT
HSYNC
HSYNC
Bits 3–4
B4 B3
Mode of Operation
0 0 Interlaced Double Serration and
(DEFAULT) Equalization
0 1 Non Interlaced Double Serration
1 0 Illegal State
1 1 Non Interlaced Single Serration and
Equalization
Double Equalization and Serration mode will output equal-
ization and serration pulses at twice the HSYNC frequency
(i.e., 2 equalization or serration pulses for every HSYNC
pulse). Single Equalization and Serration mode will output
an equalization or serration pulse for every HSYNC pulse. In
Interlaced mode equalization and serration pulses will be
output during the VBLANK period of every odd and even
field. Interlaced Single Equalization and Serration mode is
not possible with this part.
Bits 5–8
Bits 5 through 8 control the polarity of the outputs. A value of
zero in these bit locations indicates an output pulse active
LOW. A value of 1 indicates an active HIGH pulse.
B5 — VCBLANK Polarity
B6 — VCSYNC Polarity
B7 — HBLHDR Polarity
B8 — HSYNVDR Polarity
Bits 9–11
Bits 9 through 11 enable several different features of the de-
vice.
B9 — Enable Equalization/Serration Pulses (0)
Disable Equalization/Serration Pulses (1)
B10 — Disable System Clock (0)
Enable System Clock (1)
Default values for B10 are “0” in the ’ACT715/
LM1882 and “1” in the ’ACT715-R/LM1882-R.
B11 — Disable Counter Test Mode (0)
Enable Counter Test Mode (1)
This bit is not intended for the user but is for internal
testing only.
HORIZONTAL INTERVAL REGISTERS
The Horizontal Interval Registers determine the number of
clock cycles per line and the characteristics of the Horizontal
Sync and Blank pulses.
REG1 — Horizontal Front Porch
REG2 — Horizontal Sync Pulse End Time
REG3 — Horizontal Blanking Width
REG4 — Horizontal Interval Width
Line
# of Clocks per
VERTICAL INTERVAL REGISTERS
The Vertical Interval Registers determine the number of lines
per frame, and the characteristics of the Vertical Blank and
Sync Pulses.
REG5 — Vertical Front Porch
REG6 — Vertical Sync Pulse End Time
REG7 — Vertical Blanking Width
REG8 — Vertical Interval Width # of Lines per Frame
EQUALIZATION AND SERRATION PULSE
SPECIFICATION REGISTERS
These registers determine the width of equalization and ser-
ration pulses and the vertical interval over which they occur.
REG 9 — Equalization Pulse Width End Time
REG10 — Serration Pulse Width End Time
REG11 — Equalization/Serration Pulse Vertical
Interval Start Time
REG12 — Equalization/Serration Pulse Vertical
Interval End Time
VERTICAL INTERRUPT SPECIFICATION REGISTERS
These Registers determine the width of the Vertical Interrupt
signal if used.
REG13 — Vertical Interrupt Activate Time
REG14 — Vertical Interrupt Deactivate Time
CURSOR LOCATION REGISTERS
These 4 registers determine the cursor position location, or
they generate separate Horizontal and Vertical Gating sig-
nals.
REG15 — Horizontal Cursor Position Start Time
REG16 — Horizontal Cursor Position End Time
REG17 — Vertical Cursor Position Start Time
REG18 — Vertical Cursor Position End Time
Signal Specification
HORIZONTAL SYNC AND BLANK
SPECIFICATIONS
All horizontal signals are defined by a start and end time.
The start and end times are specified in number of clock
cycles per line. The start of the horizontal line is considered
pulse 1 not 0. All values of the horizontal timing registers are
referenced to the falling edge of the Horizontal Blank signal
(see Figure 1). Since the first CLOCK edge, CLOCK #1,
causes the first falling edge of the Horizontal Blank reference
pulse, edges referenced to this first Horizontal edge are n +
1 CLOCKs away, where “n” is the width of the timing in ques-
tion. Registers 1, 2, and 3 are programmed in this manner.
The horizontal counters start at 1 and count until HMAX. The
value of HMAX must be divisible by 2. This limitation is im-
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54ACT715 電子部品, 半導体
Addressing Logic (Continued)
LOAD will load the first byte of data. Auto Incrementing is
disabled on the falling edge of LOAD after ADDRDATA and
LHBYTE goes low.
Manual Addressing Mode
Cycle #
1
2
3
4
5
6
Load Falling Edge
Enable Manual Addressing
Enable Lbyte Data Load
Enable Hbyte Data Load
Enable Manual Addressing
Enable Lbyte Data Load
Enable Hbyte Data Load
Load Rising Edge
Load Address m
Load Lbyte m
Load Hbyte m
Load Address n
Load Lbyte n
Load Hbyte n
Auto Addressing Mode
Cycle #
1
2
3
4
5
6
Load Falling Edge
Enable Auto Addressing
Enable Lbyte Data Load
Enable Hbyte Data Load
Enable Lbyte Data Load
Enable Hbyte Data Load
Enable Manual Addressing
DS100232-7
Load Rising Edge
Load Start Address n
Load Lbyte (n)
Load Hbyte (n); Inc Counter
Load Lbyte (n+1)
Load Hbyte (n+1); Inc Counter
Load Address
ADDRDEC LOGIC
The ADDRDEC logic decodes the current address and gen-
erates the enable signal for the appropriate register. The en-
able values for the registers and counters change on the fall-
ing edge of LOAD. Two types of ADDRDEC logic is enabled
by 2 pair of addresses, Addresses 22 or 54 (Vectored Re-
start logic) and Addresses 23 or 55 (Vectored Clear logic).
Loading these addresses will enable the appropriate logic
and put the part into either a Restart (all counter registers are
reinitialized with preprogrammed data) or Clear (all registers
are cleared to zero) state. Reloading the same ADDRDEC
address will not cause any change in the state of the part.
The outputs during these states are frozen and the internal
DS100232-8
CLOCK is disabled. Clocking the part during a Vectored Re-
start or Vectored Clear state will have no effect on the part.
To resume operation in the new state, or disable the Vec-
tored Restart or Vectored Clear state, another
non-ADDRDEC address must be loaded. Operation will be-
gin in the new state on the rising edge of the non-ADDRDEC
load pulse. It is recommended that an unused address be
loaded following an ADDRDEC operation to prevent data
registers from accidentally being corrupted. The following
Addresses are used by the device.
Address 0
Status Register REG0
Address 1–18Data Registers REG1–REG18
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共有リンク

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部品番号部品説明メーカ
54ACT715

Programmable Video Sync Generator

National Semiconductor
National Semiconductor
54ACT715-R

Programmable Video Sync Generator

National Semiconductor
National Semiconductor


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