PDF ispLSI2064E Data sheet ( Hoja de datos )

Número de pieza	ispLSI2064E
Descripción	In-System Programmable SuperFAST High Density PLD
Fabricantes	Lattice Semiconductor
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No Preview Available ! ispLSI® 2064E In-System Programmable SuperFAST™ High Density PLD Features • SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — 2000 PLD Gates — 64 I/O Pins, Four Dedicated Inputs — 64 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic — 100% Functionally and JEDEC Upward Compatible with ispLSI 2064 Devices • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 200 MHz Maximum Operating Frequency — tpd = 4.5 ns Propagation Delay — TTL Compatible Inputs and Outputs — 5V Programmable Logic Core — ispJTAG™ In-System Programmable via IEEE 1149.1 (JTAG) Test Access Port — User-Selectable 3.3V or 5V I/O Supports Mixed Voltage Systems — PCI Compatible Outputs — Open-Drain Output Option — Electrically Erasable and Reprogrammable — Non-Volatile — Unused Product Term Shutdown Saves Power • ispLSI OFFERS THE FOLLOWING ADDED FEATURES — Increased Manufacturing Yields, Reduced Time-to- Market and Improved Product Quality — Reprogram Soldered Devices for Faster Prototyping • OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS — Complete Programmable Device Can Combine Glue Logic and Structured Designs — Enhanced Pin Locking Capability — Three Dedicated Clock Input Pins — Synchronous and Asynchronous Clocks — Programmable Output Slew Rate Control to Minimize Switching Noise — Flexible Pin Placement — Optimized Global Routing Pool Provides Global Interconnectivity • ispDesignEXPERT™ – LOGIC COMPILER AND COM- PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING — Superior Quality of Results — Tightly Integrated with Leading CAE Vendor Tools — Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms Functional Block Diagram Input Bus Output Routing Pool (ORP) B7 B6 B5 B4 A0 Global Routing Pool (GRP) B3 A1 A2 GLB A3 DQ Logic D Q Array D Q DQ A4 A5 A6 A7 Output Routing Pool (ORP) Input Bus B2 B1 B0 Description 0139/2064E The ispLSI 2064E is a High Density Programmable Logic Device. The device contains 64 Registers, 64 Universal I/O pins, four Dedicated Input Pins, three Dedicated Clock Input Pins, two dedicated Global OE input pins and a Global Routing Pool (GRP). The GRP provides com- plete interconnectivity between all of these elements. The ispLSI 2064E features 5V in-system programmabil- ity and in-system diagnostic capabilities. The ispLSI 2064E offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on the ispLSI 2064E device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. B7 (see Figure 1). There are a total of 16 GLBs in the ispLSI 2064E device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. Copyright © 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com June 2000 2064e_05 1 1 page Specifications ispLSI 2064E External Timing Parameters Over Recommended Operating Conditions PARAMETER TEST COND.4 #2 DESCRIPTION1 -200 -135 -100 UNITS MIN. MAX. MIN. MAX. MIN. MAX. tpd1 A 1 Data Prop Delay, 4PT Bypass, ORP Bypass – 4.5 – 7.5 – 10.0 ns tpd2 A 2 Data Prop Delay – 7.0 – 10.0 – 13.0 ns fmax A 3 Clk Freq with Internal Feedback3 200 – 135 – 100 – MHz fmax (Ext.) fmax (Tog.) – 4 Clk Freq with External Feedback (1 tsu2 + )tco1 – 5 Clk Frequency, Max. Toggle 133 – 100 – 77 – 200 – 143 – 100 – MHz MHz tsu1 – 6 GLB Reg Setup Time before Clk, 4 PT Bypass 3.5 – 5.0 – 6.5 – ns tco1 A 7 GLB Reg Clk to Output Delay, ORP Bypass – 3.0 – 4.0 – 5.0 ns th1 – 8 GLB Reg Hold Time after Clk, 4 PT Bypass 0.0 – 0.0 – 0.0 – ns tsu2 – 9 GLB Reg Setup Time before Clk 4.5 – 6.0 – 8.0 – ns tco2 – 10 GLB Reg Clk to Output Delay – 3.5 – 4.5 – 6.0 ns th2 – 11 GLB Reg Hold Time after Clk 0.0 – 0.0 – 0.0 – ns tr1 A 12 External Reset Pin to Output Delay – 6.0 – 10.0 – 13.5 ns trw1 – 13 External Reset Pulse Duration 3.5 – 5.0 – 6.5 – ns tptoeen B 14 Input to Output Enable – 8.0 – 12.0 – 15.0 ns tptoedis C 15 Input to Output Disable – 8.0 – 12.0 – 15.0 ns tgoeen B 16 Global OE Output Enable – 4.0 – 7.0 – 9.0 ns tgoedis C 17 Global OE Output Disable – 4.0 – 7.0 – 9.0 ns twh – 18 External Synch Clk Pulse Duration, High 2.5 – 3.5 – 5.0 – ns twl – 19 External Synch Clk Pulse Duration, Low 2.5 – 3.5 – 5.0 – ns 1. Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock. 2. Refer to Timing Model in this data sheet for further details. 3. Standard 16-bit counter using GRP feedback. 4. Reference Switching Test Conditions section. Table 2-0030A/2064E 5 5 Page Specifications ispLSI 2064E Part Number Description Device Family ispLSI 2064E – XXX X XXXX X Device Number Speed 200 = 200 MHz fmax 135 = 135 MHz fmax 100 = 100 MHz fmax ispLSI 2064E Ordering Information FAMILY ispLSI fmax (MHz) 200 135 100 tpd (ns) 4.5 7.5 10 COMMERCIAL ORDERING NUMBER ispLSI 2064E-200LT100 ispLSI 2064E-135LT100 ispLSI 2064E-100LT100 Grade Blank = Commercial Package T100 = TQFP Power L = Low 0212/2064E PACKAGE 100-Pin TQFP 100-Pin TQFP 100-Pin TQFP Table 2-0041A/2064E 11 11 Page

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