ISPLSI2064 Datasheet PDF - Lattice Semiconductor
| Part Number | ISPLSI2064 | |
| Description | In-System Programmable High Density PLD | |
| Manufacturers | Lattice Semiconductor | |
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ispLSI® 2064/A
In-System Programmable High Density PLD
Features
• ENHANCEMENTS
— ispLSI 2064A is Fully Form and Function Compatible
to the ispLSI 2064, with Identical Timing
Specifcations and Packaging
— ispLSI 2064A is Built on an Advanced 0.35 Micron
E2CMOS® Technology
• HIGH DENSITY PROGRAMMABLE LOGIC
— 2000 PLD Gates
— 64 I/O Pins, Four Dedicated Inputs
— 64 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 125 MHz Maximum Operating Frequency
— tpd = 7.5 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
— In-System Programmable (ISP™) 5V Only
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
— Lead-Free Package Options
Functional Block Diagram
Input Bus
Output Routing Pool (ORP)
B7 B6 B5 B4
A0 Global Routing Pool
(GRP)
B3
A1
A2 GLB
A3
DQ
DQ
Logic
Array D Q
DQ
A4 A5 A6 A7
Output Routing Pool (ORP)
Input Bus
B2
B1
B0
Fu
Description
0139Bisp/2064
The ispLSI 2064 and 2064A are High Density Program-
mable Logic Devices. The devices contain 64 Registers,
64 Universal I/O pins, four Dedicated Input pins, three
Dedicated Clock Input pins, two dedicated Global OE
input pins and a Global Routing Pool (GRP). The GRP
provides complete interconnectivity between all of these
elements. The 2064 and 2064A feature 5V in-system
programmability and in-system diagnostic capabilities.
The ispLSI 2064 and 2064A offer non-volatile
reprogrammability of the logic, as well as the intercon-
nect, to provide truly reconfigurable systems.
The basic unit of logic on these devices is the Generic
Logic Block (GLB). The GLBs are labeled A0, A1…B7
(Figure 1). There are a total of 16 GLBs in the ispLSI 2064
and 2064A devices. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
August 2006
2064_10
1
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Specifications ispLSI 2064/A
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER
TEST 4
COND.
#2
DESCRIPTION1
-125
-100
-80
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
tpd1
A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass – 7.5 – 10.0 – 15.0 ns
tpd2
A 2 Data Propagation Delay
– 10.0 – 13.0 – 18.5 ns
fmax
A 3 Clock Frequency with Internal Feedback 3
125 – 100 – 81.0 – MHz
fmax (Ext.)
fmax (Tog.)
–
4
Clock
Frequency
with
External
Feedback
(1
tsu2 +
)tco1
100
–
77.0
–
57.0 –
MHz
– 5 Clock Frequency, Max. Toggle
125 – 111 – 100 – MHz
tsu1
– 6 GLB Reg. Setup Time before Clock, 4 PT Bypass 5.0 – 6.5 – 9.0 – ns
tco1
A 7 GLB Reg. Clock to Output Delay, ORP Bypass
– 4.0 – 5.0 – 6.5 ns
th1
– 8 GLB Reg. Hold Time after Clock, 4 PT Bypass
0.0 – 0.0 – 0.0 –
ns
tsu2
– 9 GLB Reg. Setup Time before Clock
6.0 – 8.0 – 11.0 –
ns
tco2
– 10 GLB Reg. Clock to Output Delay
– 4.5 – 6.0 – 8.0 ns
th2 – 11 GLB Reg. Hold Time after Clock
0.0 – 0.0 – 0.0 –
ns
tr1 A 12 Ext. Reset Pin to Output Delay
– 10.0 – 13.5 – 17.0 ns
trw1
– 13 Ext. Reset Pulse Duration
5.0 – 6.5 – 10.0 –
ns
tptoeen
B 14 Product Term OE, Enable
– 12.0 – 15.0 – 18.0 ns
tptoedis
C 15 Product Term OE, Disable
– 12.0 – 15.0 – 18.0 ns
tgoeen
B 16 Global OE, Enable
– 7.0 – 9.0 – 12.0 ns
tgoedis
C 17 Global OE, Disable
– 7.0 – 9.0 – 12.0 ns
twh
– 18 External Synchronous Clock Pulse Duration, High 4.0 – 4.5 – 5.0 –
ns
twl
– 19 External Synchronous Clock Pulse Duration, Low 4.0 – 4.5 – 5.0 –
ns
1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
Table 2 - 0030B/2064-130
5
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for ISPLSI2064 electronic component. |
| Information | Total 14 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ ISPLSI2064.PDF Datasheet ] | |
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