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UCC1895 の電気的特性と機能

UCC1895のメーカーはUnitrodeです、この部品の機能は「BiCMOS Advanced Phase Shift PWM Controller」です。


製品の詳細 ( Datasheet PDF )

部品番号 UCC1895
部品説明 BiCMOS Advanced Phase Shift PWM Controller
メーカ Unitrode
ロゴ Unitrode ロゴ 




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UCC1895 Datasheet, UCC1895 PDF,ピン配置, 機能
application
INFO
available
BiCMOS Advanced Phase Shift PWM Controller
UCC1895
UCC2895
UCC3895
FEATURES
Programmable Output Turn-on Delay
Adaptive Delay Set
Bidirectional Oscillator Synchronization
Capability for Voltage Mode or Current
Mode Control
Programmable Soft Start/Soft Stop
and Chip Disable via a Single Pin
0% to 100% Duty Cycle Control
7MHz Error Amplifier
Operation to 1MHz
Low Active Current Consumption
(5mA Typical @ 500kHz)
Very Low Current Consumption
During Undervoltage Lock-out
(150µA typical)
DESCRIPTION
The UCC3895 is a phase shift PWM controller that implements control of a
full-bridge power stage by phase shifting the switching of one half-bridge
with respect to the other. It allows constant frequency pulse-width modula-
tion in conjunction with resonant zero-voltage switching to provide high effi-
ciency at high frequencies. The part can be used either as a voltage mode
or current mode controller.
While the UCC3895 maintains the functionality of the UC3875/6/7/8 family
and UC3879, it improves on that controller family with additional features
such as enhanced control logic, adaptive delay set, and shutdown capabil-
ity. Since it is built in BCDMOS, it operates with dramatically less supply
current than it’s bipolar counterparts. The UCC3895 can operate with a
maximum clock frequency of 1MHz.
The UCC3895 and UCC2895 are offered in the 20 pin SOIC (DW) pack-
age, 20 pin PDIP (N) package, 20 pin TSSOP (PW) package, and 20 pin
PLCC (Q). The UCC1895 is offered in the 20 pin CDIP (J) package, and 20
pin CLCC package (L).
SIMPLIFIED APPLICATION DIAGRAM
1 EAN
UCC3895
EAP 270
2 EAOUT
SS/DISB 19
3 RAMP
OUTA 18
4 REF
OUTB 17
5 GND
PGND 16
6 SYNC
VCC 15
7 CT
OUTC 14
8 RT
OUTD 13
9 DELAB
CS 12
10 DELCD
ADS 11
Q1
VBIAS
A
B
VOUT
C
VIN
D
SLUS157A - DECEMBER 1999
UDG-98139

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UCC1895 pdf, ピン配列
UCC1895
UCC2895
UCC3895
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, VDD=12V, RT=82k, CT=220pF, RDELAB=10k,
RDELCD=10k, CREF=0.1µF, CVDD=1.0µF, no load at outputs. TA = TJ. TA = 0°C to 70°C for UCC3895x, –40°C to +85°C for
UCC2895x, and –55°C to +125°C for UCC1895x.
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNITS
Voltage Reference Section
Output Voltage
TJ = 25°C
10V < VDD < 17.5V, 0mA < IREF < 5mA,
Temperature
4.94 5.00 5.06
4.85 5 5.15
V
V
Short Circuit Current
REF = 0V, TJ = 25°C
10 20
mA
Error Amplifier Section
Common Mode Input Voltage Range
–0.1
3.6 V
Offset Voltage
–7 7 mV
Input Bias Current (EAP, EAN)
–1 1 µA
EAOUT VOH
EAP–EAN = 500mV, IEAOUT= –0.5mA
4.0 4.5 5.0 V
EAOUT VOL
EAOUT Source Current
EAP–EAN = –500mV, IEAOUT= 0.5mA
EAP–EAN = 500mV, EAOUT= 2.5V
0 0.2 0.4 V
1.0 1.5
mA
EAOUT Sink Current
EAP–EAN = –500mV, EAOUT= 2.5V
2.5 4.5
mA
Open Loop DC Gain
75 85
dB
Unity Gain Bandwidth
(Note 3)
5.0 7.0
MHz
Slew Rate
EAN from 1V to 0V, EAP = 500mV,
EAOUT from 0.5V to 3.0V
1.5 2.2
V/µs
No Load Comparator Turn-Off Threshold
0.45 0.50 0.55 V
No Load Comparator Turn-On Threshold
0.55 0.60 0.69 V
No Load Comparator Hysteresis
0.035 0.100 0.165 V
Oscillator Section
Frequency
TJ = 25°C
473 500 527 kHz
Total Variation
Line, Temperature (Note 3)
2.5 5
%
SYNC VIH
2.05 2.10 2.25 V
SYNC VIL
1.85 1.90 1.95 V
SYNC VOH
SYNC VOL
SYNC Output Pulse Width
ISYNC = –400µA, CT = 2.6V
ISYNC = 100µA, CT = 2.6V
SYNC Load = 3.9kand 30pF in parallel
4.1 4.5 5.0 V
0.0 0.5 1.0 V
85 135 ns
RT Voltage
2.9 3 3.1 V
CT Peak Voltage
2.25 2.35 2.50 V
CT Valley Voltage
0.0 0.2 0.4 V
PWM Comparator Section
EAOUT to RAMP Input Offset Voltage
RAMP = 0V, DELAB = DELCD = REF
0.72 0.85 1.05 V
Minimum Phase Shift
(OUTA to OUTC, OUTB to OUTD)
RAMP = 0V, EAOUT = 650mV (Note 1)
0.00 0.85 1.40 %
RAMP to OUTC/OUTD Delay
RAMP from 0V to 2.5V, EAOUT = 1.2V,
DELAB = DELCD = REF (Note 2)
70 120 ns
RAMP Bias Current
RAMP < 5V, CT < 2.2V
–5 5 µA
RAMP Sink Current
RAMP = 5V, CT < 2.6V
12 19
mA
Current Sense Section
CS Bias Current
0 < CS , 2.5V, 0 < ADS < 2.5V
–4.5 20 µA
Peak Current Threshold
1.90 2.00 2.10 V
Overcurrent Threshold
2.4 2.5 2.6 V
CS to Output Delay
CS from 0 to 2.3V, DELAB = DELCD = REF
75 110 ns
3


3Pages


UCC1895 電子部品, 半導体
PIN DESCRIPTIONS (cont.)
RAMP: The Inverting Input of the PWM Comparator.
This pin receives either the CT waveform in voltage and
average current mode controls, or the current signal
(plus slope compensation) in peak current mode control.
An internal discharge transistor is provided on RAMP,
which is triggered during the oscillator dead time.
RT: Oscillator Timing Resistor. (Refer to Fig. 1, Oscillator
Block Diagram) The oscillator in the UCC3895 operates
by charging an external timing capacitor, CT, with a fixed
current programmed by RT. RT current is calculated as
follows:
I RT
= 3.0V
RT
where RT is in Ohms and IRT is in Amperes. RT can
range from 40kto 120kSoft start charging and dis-
charging current are also programmed by IRT .
SS/DISB: Soft Start/Disable. This pin combines the two
independent functions.
Disable Mode: A rapid shutdown of the chip is
accomplished by any one of the following: externally
forcing SS/DISB below 0.5V, externally forcing REF
below 4V, VDD dropping below the UNLO threshold, or
an overcurrent fault is sensed (CS = 2.5V).
In the case of REF being pulled below 4V or an UVLO
condition, SS/DISB is actively pulled to ground via an
internal MOSFET switch. If an overcurrent is sensed,
SS/DISB will sink a current of (10 IRT) until SS/DISB
falls below 0.5V.
Note that if SS/DISB is externally forced below 0.5V the
pin will start to source current equal to IRT. Also note that
the only time the part switches into the low IDD current
mode is when the part is in undervoltage lockout.
UCC1895
UCC2895
UCC3895
Soft Start Mode: After a fault or disable condition has
passed, VDD is above the start threshold, and/or
SS/DISB falls below 0.5V during a soft stop, SS/DISB
will switch to a soft start mode. The pin will now source
current, equal to IRT. A user-selected capacitor on
SS/DISB determines the soft start (and soft-start) time. In
addition, a resistor in parallel with the capacitor may be
used, limiting the maximum voltage on SS/DISB. Note
that SS/DISB will actively clamp the EAOUT pin voltage
to approximately the SS/DISB pin voltage during both
soft start, soft stop, and disable conditions.
SYNC: Oscillator Synchronization. (Refer to Fig. 1, Oscil-
lator Block Diagram) This pin is bidirectional. When used
as an output, SYNC can be used as a clock, which is the
same as the chip’s internal clock. When used as an in-
put, SYNC will override the chip’s internal oscillator and
act as it’s clock signal. This bidirectional feature allows
synchronization of multiple power supplies. The SYNC
signal will also internally discharge the CT capacitor and
any filter capacitors that are present on the RAMP pin.
The internal SYNC circuitry is level sensitive, with an in-
put low threshold of 1.9V, and an input high threshold of
2.1V. A resistor as small as 3.9kmay be tied between
SYNC and GND to reduce the sync pulse width.
VDD: Power Supply. VDD must be bypassed with a mini-
mum of a 1.0µF low ESR, low ESL capacitor to ground.
REF: 5V, ±1.2% voltage reference. The reference
supplies power to internal circuitry, and can also supply
up to 5mA to external loads. The reference is shut down
during undervoltage lock-out but is operational during all
other disable modes. For best performance, bypass with
a 0.1µF low ESR, low ESL capacitor to ground
6

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