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5100 の電気的特性と機能

5100のメーカーはIntelです、この部品の機能は「Memory Controller Hub Chipset」です。


製品の詳細 ( Datasheet PDF )

部品番号 5100
部品説明 Memory Controller Hub Chipset
メーカ Intel
ロゴ Intel ロゴ 




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5100 Datasheet, 5100 PDF,ピン配置, 機能
Intel® 5100 Memory Controller Hub
Chipset
Datasheet
July 2009
Revision 005US
Order Number: 318378-005US

1 Page





5100 pdf, ピン配列
Contents—Intel® 5100 MCH Chipset
Contents
1.0 Introduction ............................................................................................................ 22
1.1 Terminology ..................................................................................................... 22
1.2 Related Documents and Materials ........................................................................ 29
1.3 Intel® 5100 Memory Controller Hub Chipset Overview............................................ 30
2.0 Signal Description ................................................................................................... 33
2.1 Processor Front Side Bus Signals ......................................................................... 35
2.1.1 Processor Front Side Bus 0 ...................................................................... 35
2.1.2 Processor Front Side Bus 1 ...................................................................... 40
2.2 DDR2 Memory Channels ..................................................................................... 44
2.2.1 DDR2 Channel 0..................................................................................... 44
2.2.2 DDR2 Channel 1..................................................................................... 46
2.3 PCI Express* Signal List ..................................................................................... 48
2.3.1 PCI Express* Common Signals ................................................................. 48
2.3.2 PCI Express* Port 0, Enterprise South Bridge Interface (ESI) ....................... 48
2.3.3 PCI Express* Port 2 ................................................................................ 49
2.3.4 PCI Express* Port 3 ................................................................................ 49
2.3.5 PCI Express* Port 4 ................................................................................ 50
2.3.6 PCI Express* Port 5 ................................................................................ 50
2.3.7 PCI Express* Port 6 ................................................................................ 50
2.3.8 PCI Express* Port 7 ................................................................................ 51
2.3.9 PCI Express* Graphics Port...................................................................... 51
2.4 SMBus Interfaces .............................................................................................. 52
2.5 Extended Debug Port (XDP) Signal List................................................................. 53
2.6 JTAG Bus Signal List .......................................................................................... 53
2.7 Clocks, Reset and Miscellaneous .......................................................................... 54
2.8 Power and Ground Signals .................................................................................. 55
2.9 Intel® 5100 Memory Controller Hub Chipset Sequencing Requirements .................... 59
2.10 Reset Requirements........................................................................................... 60
2.10.1 Timing Diagrams .................................................................................... 60
2.10.1.1 Power-Up................................................................................. 60
2.10.1.2 Power Good ............................................................................. 61
2.10.1.3 Hard Reset............................................................................... 61
2.10.1.4 RESETI# Retriggering Limitations ............................................... 62
2.10.2 Reset Timing Requirements ..................................................................... 62
2.10.3 Miscellaneous Requirements and Limitations .............................................. 63
2.11 Intel® 5100 Memory Controller Hub Chipset Customer Reference Platform (CRP) Reset
Topology .......................................................................................................... 64
2.12 Signals Used as Straps ....................................................................................... 64
2.12.1 Functional Straps ................................................................................... 64
3.0 Register Description ................................................................................................ 65
3.1 Register Terminology ......................................................................................... 65
3.2 Platform Configuration Structure ......................................................................... 66
3.3 Routing Configuration Accesses ........................................................................... 70
3.3.1 Standard PCI Bus Configuration Mechanism ............................................... 70
3.3.2 PCI Bus 0 Configuration Mechanism .......................................................... 70
3.3.3 Primary PCI and Downstream Configuration Mechanism............................... 71
3.4 Device Mapping................................................................................................. 71
3.4.1 Special Device and Function Routing ......................................................... 72
3.5 I/O Mapped Registers ........................................................................................ 73
3.5.1 CFGADR: Configuration Address Register................................................... 73
3.5.2 CFGDAT: Configuration Data Register ....................................................... 74
July 2009
Order Number: 318378-005US
Intel® 5100 Memory Controller Hub Chipset
Datasheet
3


3Pages


5100 電子部品, 半導体
Intel® 5100 MCH Chipset—Contents
3.8.12.13HDRLOG2[7:2,0] - Header Log 2 ............................................... 163
3.8.12.14HDRLOG3[7:2,0] - Header Log 3 ............................................... 164
3.8.12.15RPERRCMD[7:2,0] - Root Port Error Command ............................ 164
3.8.12.16RPERRSTS[7:2,0] - Root Error Status Register ............................ 164
3.8.12.17RPERRSID[7:2,0] - Error Source Identification Register ................ 165
3.8.12.18SCSPCAPID[7:2,0] - Intel® 5100 Memory Controller Hub Chipset-
specific Capability ID ............................................................... 166
3.8.12.19PEX_ERR_DOCMD[7:2,0] - PCI Express* Error Do Command Register .
166
3.8.12.20EMASK_UNCOR_PEX[0] - Uncorrectable Error Detect Mask For ESI 167
3.8.12.21EMASK_UNCOR_PEX[7:2] - Uncorrectable Error Detect Mask ........ 167
3.8.12.22EMASK_COR_PEX[7:2,0] - Correctable Error Detect Mask ............. 168
3.8.12.23EMASK_RP_PEX[7:2,0] - Root Port Error Detect Mask .................. 168
3.8.12.24PEX_FAT_FERR[7:2,0] - PCI Express* First Fatal Error Register ..... 169
3.8.12.25PEX_NF_COR_FERR[7:2,0] - PCI Express* First Non-Fatal or
Correctable Error Register ........................................................ 169
3.8.12.26PEX_FAT_NERR[7:2,0] - PCI Express* Next Fatal Error Register .... 170
3.8.12.27PEX_NF_COR_NERR[7:2,0] - PCI Express* Non Fatal or Correctable
Next Error Register.................................................................. 171
3.8.12.28PEX_UNIT_FERR[7:2] - PCI Express* First Unit Error Register ....... 172
3.8.12.29PEX_UNIT_NERR[7:2] - PCI Express* Next Unit Error Register ...... 172
3.8.13 Error Registers ..................................................................................... 172
3.8.13.1 FERR_GLOBAL - Global First Error Register ................................. 173
3.8.13.2 NERR_GLOBAL - Global Next Error Register ................................ 174
3.8.13.3 FERR_FAT_FSB[1:0]: FSB First Fatal Error Register...................... 175
3.8.13.4 FERR_NF_FSB[1:0]: FSB First Non-Fatal Error Register ................ 176
3.8.13.5 NERR_FAT_FSB[1:0]: FSB Next Fatal Error Register..................... 176
3.8.13.6 NERR_NF_FSB[1:0]: FSB Next Non-Fatal Error Register ............... 176
3.8.13.7 NRECFSB[1:0]: Non Recoverable FSB Error Log Register .............. 176
3.8.13.8 RECFSB[1:0]: Recoverable FSB Error Log Register ....................... 177
3.8.13.9 NRECADDRL[1:0]: Non Recoverable FSB Address Low Error Log
Register ................................................................................. 177
3.8.13.10NRECADDRH[1:0]: Non Recoverable FSB Address High Error Log
Register ................................................................................. 177
3.8.13.11EMASK_FSB[1:0]: FSB Error Mask Register ................................ 178
3.8.13.12ERR2_FSB[1:0]: FSB Error 2 Mask Register ................................ 178
3.8.13.13ERR1_FSB[1:0]: FSB Error 1 Mask Register ................................ 178
3.8.13.14ERR0_FSB[1:0]: FSB Error 0 Mask Register ................................ 179
3.8.13.15MCERR_FSB[1:0]: FSB MCERR Mask Register.............................. 179
3.8.13.16FERR_FAT_INT - Internal First Fatal Error Register....................... 180
3.8.13.17FERR_NF_INT - Internal First Non-Fatal Error Register ................. 180
3.8.13.18NERR_FAT_INT - Internal Next Fatal Error Register ...................... 180
3.8.13.19NERR_NF_INT - Internal Next Non-Fatal Error Register................. 181
3.8.13.20NRECINT - Non Recoverable Internal Intel® 5100 Memory Controller
Hub Chipset Error Log Register ................................................. 181
3.8.13.21EMASK_INT - Internal Error Mask Register.................................. 181
3.8.13.22ERR2_INT - Internal Error 2 Mask Register ................................. 182
3.8.13.23ERR1_INT - Internal Error 1 Mask Register ................................. 182
3.8.13.24ERR0_INT - Internal Error 0 Mask Register ................................. 183
3.8.13.25MCERR_INT - Internal MCERR Mask Register............................... 183
3.9 Memory Control Registers ................................................................................. 183
3.9.1 General Registers ................................................................................. 183
3.9.1.1 MC - Memory Control Settings................................................... 183
3.9.1.2 MCA - Memory Control Settings A .............................................. 185
3.9.1.3 MS: Memory Status Register..................................................... 185
3.9.1.4 MCDEF3: MCDEF Register 3 ...................................................... 186
3.9.1.5 ERRPER: Error Period Prescaler ................................................. 186
3.9.1.6 MTR[1:0][5:0] - Memory Technology Registers ........................... 187
3.9.1.7 DMIR[1:0][4:0] - DIMM Interleave Range................................... 188
Intel® 5100 Memory Controller Hub Chipset
Datasheet
6
July 2009
Order Number: 318378-005US

6 Page



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Sockets for specific applications Solder tail

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