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NB7VQ572M の電気的特性と機能

NB7VQ572MのメーカーはON Semiconductorです、この部品の機能は「1.8V / 2.5V /3.3V Differential 4:1 Mux w/Input Equalizer to 1:2 CML Clock/Data Fanout / Translator」です。


製品の詳細 ( Datasheet PDF )

部品番号 NB7VQ572M
部品説明 1.8V / 2.5V /3.3V Differential 4:1 Mux w/Input Equalizer to 1:2 CML Clock/Data Fanout / Translator
メーカ ON Semiconductor
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NB7VQ572M Datasheet, NB7VQ572M PDF,ピン配置, 機能
NB7VQ572M
1.8V / 2.5V /3.3V Differential
4:1 Mux w/Input Equalizer
to 1:2 CML Clock/Data
Fanout / Translator
MultiLevel Inputs w/ Internal Termination
Description
The NB7VQ572M is a high performance differential 4:1 Clock /
Data input multiplexer and a 1:2 CML Clock / Data fanout buffer that
operates up to 7 GHz / 10 Gbps respectively with a 1.8 V, 2.5 V, or
3.3 V power supply.
Each INx / INx input pair incorporates a fixed Equalizer Receiver,
which when placed in series with a Data path, will enhance the
degraded signal transmitted across an FR4 backplane or cable
interconnect. For applications that do not require Equalization,
consider the NB7V572M, which is pincompatible to the
NB7VQ572M.
The differential Clock / Data inputs have internal 50 W termination
resistors and will accept differential LVPECL, CML, or LVDS logic
levels. The NB7VQ572M incorporates a pair of Select pins that will
choose one of four differential inputs and will produce two identical
CML output copies of Clock or Data.
As such, the NB7VQ572M is ideal for SONET, GigE, Fiber
Channel, Backplane and other Clock/Data distribution applications.
The two differential CML outputs will swing 400 mV when externally
loaded and terminated with a 50 W resistor to VCC and are optimized
for low skew and minimal jitter.
The NB7VQ572M is offered in a low profile 5x5 mm 32pin QFN
PbFree package. Application notes, models, and support
documentation are available at www.onsemi.com. The NB7VQ572M
is a member of the GigaCommfamily of high performance clock
products.
http://onsemi.com
MARKING
DIAGRAM
1 32
QFN32
MN SUFFIX
CASE 488AM
1
NB7V
Q572M
AWLYYWWG
G
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = PbFree Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 10 of
this data sheet.
Features
Input Data Rate > 10 Gb/s Typical
Data Dependent Jitter < 10 ps
Maximum Input Clock Frequency > 6 GHz Typical
Random Clock Jitter < 0.8 ps RMS
Low Skew 1:2 CML Outputs, < 15 ps max
4:1 MultiLevel Mux Inputs, accepts LVPECL, CML,
LVDS
175 ps Typical Propagation Delay
45 ps Typical Rise and Fall Times
Differential CML Outputs, 400 mV PeaktoPeak,
Typical
Operating Range: VCC = 1.71 V to 3.6 V with GND =
0V
Internal 50 W Input Termination Resistors
VREFAC Reference Output
QFN32 Package, 5mm x 5mm, PbFree
40°C to +85°C Ambient Operating Temperature
These are PbFree Devices
© Semiconductor Components Industries, LLC, 2010
October, 2010 Rev. P0
1
Publication Order Number:
NB7VQ572M/D

1 Page





NB7VQ572M pdf, ピン配列
NB7VQ572M
Table 2. PIN DESCRIPTION
Pin Number Pin Name
I/O
Pin Description
1, 4
5, 8
25, 28
29, 32
IN0, IN0
IN1, IN1
IN2, IN2
IN3, IN3
LVPECL, CML, Noninverted, Inverted, Differential Clock or Data Inputs
LVDS Input
2, 6
26, 30
VT0, VT1
VT2, VT3
Internal 100 W Centertapped Termination Pin for INx / INx
15
18
14, 19
SEL0
SEL1
NC
LVTTL/LVCMOS
Input
Input Select pins, default HIGH when left open through a 94 kW pullup resistor. Input
logic threshold is VCC/2. See Select Function, Table 1.
No Connect
10, 13, 16
17, 20, 23
VCC
Positive Supply Voltage.
11, 12
21, 22
Q0, Q0
Q1, Q1
CML Output
Inverted, Noninverted Differential Outputs.
9, 24
GND
Negative Supply Voltage
3 VREFAC0
7 VREFAC1
27 VREFAC2
31 VREFAC3
Output Voltage Reference for CapacitorCoupled Inputs
EP
The Exposed Pad (EP) on the QFN32 package bottom is thermally connected to the
die for improved heat transfer out of package. The exposed pad must be attached to
a heatsinking conduit. The pad is electrically connected to the die, and must be
electrically connected to GND.
1. In the differential configuration when the input termination pins (VT0, VT1, VT2, VT3) are connected to a common termination voltage or left
open, and if no signal is applied on INx/INx input, then the device will be susceptible to selfoscillation.
2. All VCC, and GND pins must be externally connected to a power supply for proper operation.
http://onsemi.com
3


3Pages


NB7VQ572M 電子部品, 半導体
NB7VQ572M
Table 6. AC CHARACTERISTICS VCC = 1.71 V to 3.6 V, GND = 0 V, TA = 40°C to +85°C (Note 11)
Symbol
Characteristic
Min Typ Max Unit
fMAX
Maximum Input Clock Frequency
VOUT w 200 mV
6
7
GHz
fDATAMAX Maximum Operating Data Rate
NRZ, (PRBS23)
10
11
Gbps
fSEL Maximum Toggle Frequency, SELx
4 10
MHz
VOUTPP
Output Voltage Amplitude (@ VINPPmin) (Note 12) (Figure 12)
fin 5 GHz
250
400
mV
tPLH,
Propagation Delay to Differential
@ 1 GHz INx/INx to Qx/Qx
100
175
250
tPHL
Outputs Measured at Differential
@ 50 MHz SELx to Qx
7 20
Crosspoint
ps
ns
tPD Tempco
tskew
tDC
FN
Differential Propagation Delay Temperature Coefficient
Output Output skew (within device) (Note 13)
Device Device skew (tpdmax tpdmin)
Output Clock Duty Cycle (Reference Duty Cycle = 50%)
fIN v 5 GHz
Phase Noise, fin = 1 GHz
10 kHz
100 kHz
1 MHz
10 MHz
20 MHz
40 MHz
45
50
0
30
50
134
136
149
149
149
149
Dfs/°C
15 ps
100
%
55
dBc
tŐFN
Integrated Phase Jitter (Figure TBD) fin = 1 GHz, 12 kHz 20 MHz
Offset (RMS)
35
fs
tJITTER
Random Clock Jitter, RJ (Note 14)
Deterministic Jitter, DJ (Note 15)
fin 6 GHz
fin 10 Gbps (12” FR4)
Crosstalk Induced Jitter (Adjacent Channel) (Note 17)
0.2 0.8 ps RMS
10 ps pkpk
0.7 ps RMS
VINPP
Input Voltage Swing (Differential Configuration) (Note 16)
100
1200
mV
tr,, tf
Output Rise/Falltimes @ 1 GHz; (20% 80%), VIN = 400 mV Qx, Qx
25
45
65
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Measured using a 150 mVpkpk source, 50% duty cycle clock source. All output loading with external 50 W to VCC. Input edge rates
40 ps (20% 80%).
12. Output voltage swing is a singleended measurement operating in differential mode.
13. Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation when
the delays are measured from crosspoint of the inputs to the crosspoint of the outputs.
14. Additive RMS jitter with 50% duty cycle clock signal.
15. Additive PeaktoPeak data dependent jitter with input NRZ data at PRBS23.
16. Input voltage swing is a singleended measurement operating in differential mode.
17. Crosstalk is measured at the output while applying two similar clock frequencies that are asynchronous with respect to each other at the
inputs.
http://onsemi.com
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部品番号部品説明メーカ
NB7VQ572M

1.8V / 2.5V /3.3V Differential 4:1 Mux w/Input Equalizer to 1:2 CML Clock/Data Fanout / Translator

ON Semiconductor
ON Semiconductor


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