|
|
NB3F8L3005CのメーカーはON Semiconductorです、この部品の機能は「3.3V / 2.5V / 1.8V / 1.5V 2:1:5 LVCMOS Fanout Buffer」です。 |
部品番号 | NB3F8L3005C |
| |
部品説明 | 3.3V / 2.5V / 1.8V / 1.5V 2:1:5 LVCMOS Fanout Buffer | ||
メーカ | ON Semiconductor | ||
ロゴ | |||
このページの下部にプレビューとNB3F8L3005Cダウンロード(pdfファイル)リンクがあります。 Total 13 pages
NB3F8L3005C
3.3V / 2.5V / 1.8V / 1.5V
2:1:5 LVCMOS Fanout Buffer
Description
The NB3F8L3005C is a 2:1:5 Clock / Data fanout buffer operating
on a 3.3 V / 2.5 V Core VDD and two flexible 3.3 V / 2.5 V / 1.8 V /
1.5 V VDDOx supplies which must be equal or less than VDD.
A Mux selects between a Crystal input, or a differential/SE Clock /
Data inputs. Differential Inputs accept LVPECL, LVDS, HCSL, or
SSTL and Single−Ended levels. The MUX control line, SEL selects
CLK/CLK, or Crystal input pins per Table 3. The Crystal input is
disabled when a Clock input is selected. Output enable pin, OE,
synchronously forces a High Impedance state (Hi−Z) when Low per
Table 4.
Outputs consist of five single−ended LVCMOS outputs.
www.onsemi.com
QFN24
G SUFFIX
CASE 485DJ
MARKING
DIAGRAM
1
NB3F8L
3005C
ALYWG
G
Features
• Five LVCMOS / LVTTL Outputs up to 200 MHz
• Differential Inputs Accept LVPECL, LVDS, HCSL, SSTL, or
LVCMOS/LVTTL
• Crystal Interface
• Crystal Input Frequency Range: 10 MHz to 50 MHz
• Output Skew: 10 ps Typical
• Additive RMS Phase Jitter @ 156.25 MHz, (12 kHz – 20 MHz):
0.03 ps (Typical)
• Synchronous Output Enable
• Output Defined Level When Input is Floating
• Power Supply Modes:
♦ Single 3.3 V ± 5%
♦ Single 2.5 V ± 5%
♦ Mixed 3.3 V ± 5% Core/2.5 V ± 5% Output Operating Supply
♦ Mixed 3.3 V ± 5% Core/1.8 V ± 0.2 V Output Operating Supply
♦ Mixed 3.3 V ± 5% Core/1.5 V ± 0.15 V Output Operating Supply
♦ Mixed 2.5 V ± 5% Core/ 1.8 V ± 0.2 V Output Operating Supply
♦ Mixed 2.5 V ± 5% Core /1.5 V ± 0.15 V Output Operating Supply
• Two Separate Output Bank Power Supplies
• Industrial Temperature Range: −40°C to 85°C
• These are Pb−Free Devices
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 12 of
this data sheet.
Applications
• Clock Distribution
• Networking and Communications
• High End Computing
• Wireless and Wired Infrastructure
End Products
• Servers
• Ethernet Switch/Routers
• ATE
• Test and Measurement
© Semiconductor Components Industries, LLC, 2015
April, 2015 − Rev. 1
1
Publication Order Number:
NB3F8L3005C/D
1 Page NB3F8L3005C
Table 1. PIN DESCRIPTION
Number
Name
Type
Input
Default
Description
3, 5 Q0, Q1
LVCMOS
Outputs − Bank A
13, 15, 17 Q2, Q3, Q4
LVCMOS
Outputs − Bank B
2, 6 VDDOA
Power
Positive Supply Pins for Bank A Outputs Q0 − Q1
14, 18
VDDOB
Power
Positive Supply Pins for Bank B Outputs Q2 − Q4
1, 4, 7, 11,
12, 16, 19
GND
GND
Ground Supply
8, 23
9
VDD
XTAL_IN
Power
XTAL OSC / CLK Input
VDD Positive Supply pin for Core and Inputs.
Crystal Oscillator Interface or External Clock Source at
LVCMOS Levels
10
XTAL_OUT
XTAL OSC Output
Crystal Interface
20 CLK
Diff / SE Input
Pullup /
Pulldown
Inverting differential clock input
21 CLK
Diff / SE Input
Pulldown
Non-inverting clock input
22
SEL
LVCMOS / LVTTL
Pulldown
Input clock select. See Table 3 for function. Input Pulldown
Input
24
OE
LVCMOS / LVTTL
Pulldown
Output Enable Control. See Table 4 for function.
Input
− EP
−
The Exposed Pad (EP) on the QFN−24 package bottom is
thermally connected to the die for improved heat transfer out
of package. The exposed pad must be attached to a heat−
sinking conduit. The pad is electrically connected to the die,
and must be electrically connected to GND.
1. All VDD, VDDOx and GND pins must be externally connected to a power supply to guarantee proper operation. Bypass each VDD and VDDOx
with 0.01 mF CAP to GND.
Table 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN Input Capacitance
RPU Input Pullup Resistor
RPD Input Pulldown Resistor
CPD Power Dissipation Capacitance (per output)
VDDO = 3.3 V
VDDO = 2.5 V
VDDO = 1.8 V
VDDO = 1.5 V
ROUT
Output Impedance
VDDO = 3.3 V
VDDO = 2.5 V
VDDO = 1.8 V
VDDO = 1.5 V
Min Typ Max Unit
4 pF
50 kW
50 kW
pF
W
20
www.onsemi.com
3
3Pages NB3F8L3005C
Table 11. AC CHARACTERISTICS VDD ≥ VDDO; VDD = 3.3 V ± 5% (3.135 V to 3.465 V) or VDD = 2.5 V ±5% (2.375 V to 2.625 V)
and VDDOx = 3.3 V ± 5% (3.135 V to 3.465 V) or 2.5 V ± 5% (2.375 V to 2.625 V) or 1.8 V ± 0.2 V (1.6 V to 2.0 V) or 1.5 V ± 0.15 V
(1.35 V to 1.65 V); TA = −40°C to 85°C
Symbol
Parameter
Test Conditions
Min Typ Max Unit
fMAX
Output Frequency Using External
Crystal
10 50 MHz
Using External
Clock Source
(Note 4)
DC 200 MHz
tsk(o)
tJITTERF
tR / tF
odc
PSRR
tEN
Output Skew (Notes 5 and 6)
Additive RMS
Phase Jitter
(Integrated
12 kHz − 20 MHz)
fC = 156.25 MHz
Input clock from
CLK/CLK
External clock
over drives
crystal interface
Input clock from
crystal
Output Rise/Fall Time (20% and 80%)
CL = 10 pF
Output Duty Cycle
Power Supply
Ripple Rejection
Output Enable
Time (Note 7)
OE
VDDOx = 3.3 V ± 5%
VDDOx = 2.5 V ± 5%
VDDOx = 1.8 V ± 0.2 V
VDDOx = 1.5 V ± 0.15 V
VDDOx = 3.3 V ± 5%
VDDOx = 2.5 V ± 5%
VDDOx = 1.8 V ± 0.2 V
VDDOx = 1.5 V ± 0.15 V
VDDOx = 3.3 V ± 5%
VDDOx = 2.5 V ± 5%
VDDOx = 1.8 V ± 0.2 V
VDDOx = 1.5 V ± 0.15 V
VDDOx = 3.3 V ± 5%
VDDOx = 2.5 V ± 5%
VDDOx = 1.8 V ± 0.2 V
VDDOx = 1.5 V ± 0.15 V
VDDOx = 3.3 V ± 5%
VDDOx = 2.5 V ± 5%
VDDOx = 1.8 V ± 0.2 V
VDDOx = 1.5 V ± 0.15 V
100 kHz, 100 mVPP
Ripple Injected on VDD,
VDDO = 2.5 V
10 25 ps
0.03 ps
0.03
0.03
0.03
0.03
0.03
0.03
0.03
0.03
0.03
0.03
0.03
150 350 500
ps
150 350 500
150 350 600
150 350 600
45 55 %
40 60
40 60
40 60
−44 dBc
4 cycles
tDIS
Output Disable
OE
Time (Note 7)
4 cycles
MUX_ISOLATION MUX_ISOLATION
155.52 MHz
55
dB
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
4. XTAL_IN can be overdriven relative to a signal a crystal would provide.
5. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDOx/2.
6. This parameter is defined in accordance with JEDEC Standard 65.
7. These parameters are guaranteed by characterization. Not tested in production. See Parameter Measurement Information
8. AC parameters for LVCMOS are dependent upon output capacitive loading.
www.onsemi.com
6
6 Page | |||
ページ | 合計 : 13 ページ | ||
|
PDF ダウンロード | [ NB3F8L3005C データシート.PDF ] |
データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
部品番号 | 部品説明 | メーカ |
NB3F8L3005C | 3.3V / 2.5V / 1.8V / 1.5V 2:1:5 LVCMOS Fanout Buffer | ON Semiconductor |