DataSheet.jp

NB3F8L3010C の電気的特性と機能

NB3F8L3010CのメーカーはON Semiconductorです、この部品の機能は「3.3V / 2.5V / 1.8V / 1.5V 3:1:10 LVCMOS Fanout Buffer」です。


製品の詳細 ( Datasheet PDF )

部品番号 NB3F8L3010C
部品説明 3.3V / 2.5V / 1.8V / 1.5V 3:1:10 LVCMOS Fanout Buffer
メーカ ON Semiconductor
ロゴ ON Semiconductor ロゴ 




このページの下部にプレビューとNB3F8L3010Cダウンロード(pdfファイル)リンクがあります。

Total 13 pages

No Preview Available !

NB3F8L3010C Datasheet, NB3F8L3010C PDF,ピン配置, 機能
NB3F8L3010C
3.3V / 2.5V / 1.8V / 1.5V
3:1:10 LVCMOS Fanout Buffer
Description
The NB3F8L3010C is a 3:1:10 Clock / Data fanout buffer operating
on a 3.3 V / 2.5 V Core VDD and two flexible 3.3 V / 2.5 V / 1.8 V /
1.5 V VDDOn supplies which must be equal or less than VDD.
A Mux selects between a Crystal input, or either of two
differential/SE Clock / Data inputs. Differential Inputs accept
LVPECL, LVDS, HCSL, or SSTL and Single−Ended levels. The
MUX control lines, SEL0 and SEL1, select CLK0/CLK0,
CLK1/CLK1, or Crystal input pins per Table 3. The Crystal input is
disabled when a Clock input is selected. Output enable pin, OE,
synchronously forces a High Impedance state (HZ) when Low per
Table 4.
Outputs consist of 10 single−ended LVCMOS outputs.
Features
Ten CMOS / LVTTL Outputs up to 200 MHz
Differential Inputs Accept LVPECL, LVDS, HCSL, or SSTL
Crystal Oscillator Interface
Crystal Input Frequency Range: 10 MHz to 50 MHz
Output Skew: 10 ps Typical
Additive RMS Phase Jitter @ 125 MHz, (12 kHz – 20 MHz): 0.03 ps
(Typical)
Synchronous Output Enable
Output Defined Level When Input is Floating
Power Supply Modes:
Single 3.3 V
Single 2.5 V
Mixed 3.3 V ± 5% Core/2.5 V ± 5% Output Operating Supply
Mixed 3.3 V ± 5% Core/1.8 V ± 0.2 V Output Operating Supply
Mixed 3.3 V ± 5% Core/1.5 V ± 0.15 V Output Operating Supply
Mixed 2.5 V ± 5% Core/ 1.8 V ± 0.2 V Output Operating Supply
Mixed 2.5 V ± 5% Core /1.5 V ± 0.15 V Output Operating Supply
Two Separate Output Bank Power Supplies
Industrial temp. range -40°C to 85°C
These are Pb−Free Devices
Applications
Clock Distribution
Networking and Communications
High End Computing
Wireless and Wired Infrastructure
End Products
Servers
Ethernet Switch/Routers
ATE
Test and Measurement
www.onsemi.com
1 32
QFN32
G SUFFIX
CASE 488AM
MARKING
DIAGRAM
1
NB3F8L
3010C
AWLYYWWG
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information page 12 of this
data sheet.
© Semiconductor Components Industries, LLC, 2016
May, 2016 − Rev. 7
1
Publication Order Number:
NB3F8L3010C/D

1 Page





NB3F8L3010C pdf, ピン配列
NB3F8L3010C
Table 1. PIN DESCRIPTION
Number
Name
Type
Input
Default
Description
1, 3, 5, 7,
8
Q0, Q1, Q2,
Q3, Q4
LVCMOS
Outputs − Bank A
17, 18,
20, 22, 24
Q5, Q6, Q7,
Q8, Q9
LVCMOS
Outputs − Bank B
2, 6 VDDOA
Power
Positive Supply Pins for Bank A Outputs Q0 − Q4
19, 23
VDDOB
Power
Positive Supply Pins for Bank B Outputs Q5 − Q9
4, 9, 15,
16, 21,
25, 26, 32
GND
GND
Ground Supply
10 VDD
Power
11
XTAL_IN
XTAL OSC / CLK Input
VDD Positive Supply pin for Core and Inputs.
Crystal Oscillator Interface or External Clock Source at
LVCMOS Levels
12
XTAL_OUT
XTAL OSC Output
Crystal Oscillator Interface
13 CLK0
Diff / SE Input
Pulldown
Non-inverting clock/data input 0.
14 CLK0
Diff / SE Input
Pullup /
Pulldown
Inverting differential clock input 0.
27 CLK1
Diff / SE Input
Pullup /
Pulldown
Inverting differential clock input 1
28 CLK1
Diff / SE Input
Pulldown
Non-inverting clock/data input 1
29
SEL1
LVCMOS / LVTTL
Pulldown
Input clock select. See Table 3 for function. Input Pulldown
Input
30
SEL0
LVCMOS / LVTTL
Pulldown
Input clock select. See Table 3 for function. Input Pulldown
Input
31
OE
LVCMOS / LVTTL
Pulldown
Output Enable Control. See Table 4 for function.
Input
− EP
The Exposed Pad (EP) on the QFN−32 package bottom is
thermally connected to the die for improved heat transfer out
of package. The exposed pad must be attached to a heat−
sinking conduit. The pad is electrically connected to the die,
and must be electrically connected to GND.
1. All VDD, VDDOn and GND pins must be externally connected to a power supply to guarantee proper operation. Bypass each VDD and VDDOn
with 0.01 mF CAP to GND.
Table 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN Input Capacitance
R Input Pulldown Resistor; Input Pulldown Resistor
CPD Power Dissipation Capacitance (per output)
VDDO = 3.3 V
VDDO = 2.5 V
VDDO = 1.8 V
VDDO = 1.5 V
ROUT
Output Impedance
VDDO = 3.3 V
VDDO = 2.5 V
VDDO = 1.8 V
VDDO = 1.5 V
Min Typ Max Unit
4 pF
50 kW
pF
W
20
www.onsemi.com
3


3Pages


NB3F8L3010C 電子部品, 半導体
NB3F8L3010C
Table 11. AC CHARACTERISTICS VDD = 3.3 V ± 5% (3.135 V to 3.465 V) or VDD = 2.5 V ±5% (2.375 V to 2.625 V) and
VDDOn = 3.3 V ± 5% (3.135 V to 3.465 V) or 2.5 V ± 5% (2.375 V to 2.625 V) or 1.8 V ± 0.2 V (1.6 V to 2.0 V) or 1.5 V ± 0.15 V (1.35 V
to 1.65 V); TA = −40°C to 85°C
Symbol
Parameter
Test Conditions
Min Typ Max Unit
tsk(o)
tJITTERF
tR / tF
odc
tEN
Output Skew (Notes 6 and 7)
Additive RMS
Phase Jitter
(Integrated
12 kHz *
20 MHz)
(Note 8)
Input clock from
CLK0/CLK0 or
CLK1/CLK1
External clock
over drives
crystal interface
Input clock from
crystal
Output Rise/Fall Time (20% and 80%)
Output Duty Cycle
Output Enable
Time (Note 9)
OE
VDDOn = 3.3 V ± 5%
VDDOn = 2.5 V ± 5%
VDDOn = 1.8 V ± 0.2 V
VDDOn = 1.5 V ± 0.15 V
VDDOn = 3.3 V ± 5%
VDDOn = 2.5 V ± 5%
VDDOn = 1.8 V ± 0.2 V
VDDOn = 1.5 V ± 0.15 V
VDDOn = 3.3 V ± 5%
VDDOn = 2.5 V ± 5%
VDDOn = 1.8 V ± 0.2 V
VDDOn = 1.5 V ± 0.15 V
VDDOn = 3.3 V ± 5%
VDDOn = 2.5 V ± 5%
VDDOn = 1.8 V ± 0.2 V
VDDOn = 1.5 V ± 0.15 V
VDDOn = 3.3 V ± 5%
VDDOn = 2.5 V ± 5%
VDDOn = 1.8 V ± 0.2 V
VDDOn = 1.5 V ± 0.15 V
10 55 ps
0.03 ps
0.03
0.03
0.03
0.03
0.03
0.03
0.03
0.03
0.03
0.03
0.03
150 350 500
ps
150 350 500
150 350 600
150 350 600
45 55 %
40 60
40 60
40 60
4 cycles
tDIS
Output Disable
OE
Time (Note 9)
4 cycles
MUX_ISOLATION MUX_ISOLATION
155.52 MHz
55
dB
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
5. XTAL_IN can be overdriven relative to a signal a crystal would provide.
6. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDOn/2.
7. This parameter is defined in accordance with JEDEC Standard 65.
8. See phase noise plot.
9. These parameters are guaranteed by characterization. Not tested in production. See Parameter Measurement Information
www.onsemi.com
6

6 Page



ページ 合計 : 13 ページ
 
PDF
ダウンロード
[ NB3F8L3010C データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
NB3F8L3010C

3.3V / 2.5V / 1.8V / 1.5V 3:1:10 LVCMOS Fanout Buffer

ON Semiconductor
ON Semiconductor


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap