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MT90810AK3 の電気的特性と機能

MT90810AK3のメーカーはZarlink Semiconductorです、この部品の機能は「Flexible MVIP Interface Circuit」です。


製品の詳細 ( Datasheet PDF )

部品番号 MT90810AK3
部品説明 Flexible MVIP Interface Circuit
メーカ Zarlink Semiconductor
ロゴ Zarlink Semiconductor ロゴ 




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MT90810AK3 Datasheet, MT90810AK3 PDF,ピン配置, 機能
CMOS MT90810
Flexible MVIP Interface Circuit
Data Sheet
Features
• MVIPand ST-BUScompliant
• MVIP Enhanced Switching with 384x384 channel
capacity (256 MVIP channels; 128 local
channels)
• On-chip PLL for MVIP master/slave operation
• Local output clocks of 2.048,4.096,8.192 MHz
with programmable polarity
• Local serial interface is programmable to 2.048,
4.096 or 8.192 Mb/s with associated clock
outputs
• Additional control output stream
• Per-channel message mode
• Two independently programmable groups of up to
12 framing signals each
• Motorola non-multiplexed or Intel
multiplexed/non-multiplexed microprocessor
interface
Applications
• Medium size digital switch matrices
• MVIP interface functions
• Serial bus control and monitoring
August 2005
Ordering Information
MT90810AK3 100 Pin PQFP*
*Pb Free Sn-Bi Plating
Trays
0°C to +70°C
• Centralized voice processing systems
• Voice/Data multiplexer
Description
Zarlink’s MT90810 is a Flexible MVIP Interface Circuit
(FMIC). The MVIP (Multi-Vendor Integration Protocol)
compliant device provides a complete MVIP compliant
interface between the MVIP Bus and a wide variety of
processors, telephony interfaces and other circuits. A
built-in digital time-slot switch provides MVIP enhanced
switching between the full MVIP Bus and any
combination of up to 128 full duplex local channels of
64 kbps each. An 8 bit microprocessor port allows real-
time control of switching and programming of device
configuration. On-board clock circuitry, including both
analog and digital phase-locked loops, supports all
MVIP clock modes. The local interface supports PCM
rates of 2.048, 4.096 and 8.192 Mb/s, as well as
parallel DMA through the microprocessor port.
SEC8K
C4b
C2o
F0b
DSo[0:7]
DSi[0:7]
LDO[0:3]
LDI[0:3]
TCK
TMS
TDI
TDO
EX_8KA EX_8KB X2 X1/CLKIN PLL_LO PLL_LI FRAME
Timing and Clock Control
(Oscillator and Analog & Digital PLLs)
Enhanced Switch
S-P/ Data Memory
P-S
Connection Memory
Programmable
Framing Signals
JTAG
Microprocessor Interface
CLK2
CLK4
CLK8
RESET
CSTo
FGA[0:11]
FGB[0:11]
ERR
AD[0:7] A[0:1] ALE WR/ RD/ CS RDY/ DREQ[0:1] DACK[0:1]
R/W DS
DTACK
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1997-2005, Zarlink Semiconductor Inc. All Rights Reserved.

1 Page





MT90810AK3 pdf, ピン配列
MT90810
Data Sheet
Pin Description
Pin #
58, 60,
63, 67,
70, 72,
74, 77
59, 61,
64, 68,
71, 73,
75, 78
80, 82,
83, 85
87, 88,
89, 90
4
55
56
54
53
91
92
94
95
97
98
100, 1,
2, 3, 5,
20, 33,
46, 57,
69, 81,
96
6, 7, 8,
9, 14,
28, 39,
51, 62,
76, 84,
99
Name
DSo[0:7]
Description
MVIP DSo Streams (Bidirectional CMOS). 2.048 Mb/s serial data streams conforming
to ST-BUS serial data stream specifications.
DSi[0:7] MVIP DSi Streams (Bidirectional CMOS). 2.048 Mb/s serial data streams conforming to
ST-BUS serial data stream specifications.
LDO[0:3]
LDI[0:3]
CSTo
F0b
C4b
C2o
SEC8K
EX_8KA
EX_8KB
FRAME
CLK8
CLK4
CLK2
FGA[0:11]
Local Output Serial Streams (Output). Serial data streams programmable to 2.048,
4.096 or 8.192 Mb/s data rates.
Local Input Serial Streams (TTL Input). Serial data streams programmable to 2.048,
4.096 or 8.192 Mb/s data rates.
Control ST-BUS Output (Output). This is a 1.024 Mb/s output. The state of each bit in
this stream is determined by the CSTo bit in connection memory high.
MVIP F0 signal (CMOS Input/Output). ST-BUS 8 kHz framing signal
MVIP C4 signal (CMOS Input/Output). ST-BUS 4.096 MHz clock
MVIP C2 signal (Output). ST-BUS 2.048 MHz clock. This pin is automatically set to
high impedance when it is not driven.
MVIP SEC8K signal (CMOS Input/Output). A secondary 8 kHz signal used either as
an input source to the on-chip digital PLL or as an output to the MVIP bus.
External 8 kHz input A (TTL Input).
External 8 kHz input B (TTL Input).
Local Frame Output Signal (Output). This 8 kHz framing signal has a duty cycle and
period equal to the MVIP F0 signal.
8 MHz Local Output Clock (Output). This is a 8 MHz clock.
4 MHz Local Output Clock (Output). This 4 MHz clock has a duty cycle and period equal
to the MVIP C4 signal.
2 MHz Local Output Clock (Output). This 2 MHz clock has a duty cycle and period equal
to the MVIP C2 signal.
Frame Group A framing signals (Output). Programmable framing signals. The frame
group outputs are determined by mode bits in the frame register to be either
programmed outputs, output drive enables for DSo, or output framing pulses for use
with local serial data streams.
FGB[0:11]
Frame Group B framing signals (Output). Programmable framing signals. The frame
group outputs are determined by mode bits in the frame register to be either
programmed outputs, output drive enables for DSi, or output framing pulses for use with
local serial data streams.
3
Zarlink Semiconductor Inc.


3Pages


MT90810AK3 電子部品, 半導体
MT90810
Data Sheet
the FMIC and an output holding register an shift register make up the parallel to serial conversion blocks on the
output of the FMIC.
Data Memory
Data memory is a 384 byte static RAM block which provides one sample of buffering for each of the 384 channels.
An input shift register and holding latch for each input stream make up the serial to parallel conversion blocks on
the input. Each input channel is mapped to a unique location in the RAM, as shown Table 18 - “Data Memory
Mapping”.
Data memory can be read and written by the microprocessor (See “Software Control” for further details). Note that
writing to data memory may be futile since the contents will be overwritten by incoming data on the serial input
streams.
Connection Memory
Connection memory is comprised of a static RAM block 384 locations by 12 bits. Each location in connection
memory corresponds to one of the 384 output channels. The mapping of memory location to output channel is the
same as the mapping of input channel to data memory location and is shown in Table 19 - “Connection Memory
Mapping”.
The lower 8 bits of connection memory form connection memory low byte as shown in Figure 10 - “Connection
Memory Low Byte”. The bits are defined in Table 20, “Connection Memory Low Bits”.
The upper 4 bits of connection memory form connection memory high (refer to Figure 11 - “Connection memory
high byte”). Connection memory low byte, together with the least significant bit of connection memory high form an
address to point to in data memory. The location pointed to in data memory provides the data for a given output
channel. The remaining three bits in connection memory high are control bits. These bits perform slightly different
functions for MVIP and local channels. The control bits in connection memory high for MVIP streams enable/disable
output drivers, specify message or connection mode for individual output channels, and determine the direction of
the DSi/DSo channel pair (see Table 21 - “Connection Memory High Bits for MVIP channels” for further details). The
control bits in connection memory high for local streams enable/disable DMA transfer, specify message or
connection mode for individual output channels, and control CSTo timing (see Table 22 - “Connection Memory High
Bits for Local channels” for further details).
Connection memory can be read and written by the microprocessor (see “Software Control” for further details).
When writing to connection memory, it is necessary to first write the low bits and then the high bits. The low bits are
held in a temporary register until the high bits are written. The complete write of all 12 bits (to connection memory)
is only performed when the high bits are being written.
Connection and Message Modes
In connection mode, the connection memory low byte and the least significant bit of connection memory high form
a 9 bit address to point to in data memory. The location pointed to specifies which source/input channel to connect
to the respective output channel and stream. The same source channel can be routed to various output channels,
thus providing broadcast facility within the switch.
In message mode, the connection memory low byte is sent directly out the corresponding output channel and
stream. The least significant bit of connection memory high is not used.
Direction Control Bit
The direction control (DC) bit in connection memory high determines the direction of the associated DSi-DSo
channel pair. If the DSi or DSo channel is programmed as an input, the corresponding DSo or DSi channel will
automatically be configured as an output. Thus, there are always 256 MVIP input and 256 MVIP output channels or
256 full duplex MVIP channels on the MVIP bus. Figure 3 - “Per channel direction control” illustrates the use of DC
6
Zarlink Semiconductor Inc.

6 Page



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部品番号部品説明メーカ
MT90810AK3

Flexible MVIP Interface Circuit

Zarlink Semiconductor
Zarlink Semiconductor


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