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PDF MT7688 Data sheet ( Hoja de datos )
| Número de pieza | MT7688 | |
| Descripción | 1T1R 802.11n Wi-Fi radio / 580MHz MIPS 24KEc CPU | |
| Fabricantes | MEDIATEK | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MT7688 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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MediaTek MT7688 Datasheet
Version: 1.4
Release date: 15th April 2016
© 2016 MediaTek Inc.
This document contains information that is proprietary to MediaTek Inc. (“MediaTek”) and/or its licensor(s).
MediaTek cannot grant you permission for any material that is owned by third parties. You may only use or
reproduce this document if you have agreed to and been granted explicit permission within the “License
Agreement” that is available on MediaTek’s website (“Permitted User”). If you are not a Permitted User,
please cease any access or use of this document immediately. Any unauthorized use, reproduction or
disclosure of this document in whole or in part is strictly prohibited. For more information, please consult your
legal advisor. Specifications contained herein are subject to change without notice.
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MediaTek MT7688 Datasheet
5.14.4 PCM CONFIGURATION
5.14.5 REGISTER
5.15 GENERIC DMA CONTROLLER
5.15.1 FEATURES
5.15.2 BLOCK DIAGRAM
5.15.3 PERIPHERAL CHANNEL CONNECTION
5.15.4 REGISTERS
5.16 AES CONTROLLER
5.16.1 REGISTERS
5.17 PWM (PULSE WIDTH MODULATION)
5.17.1 REGISTERS
5.18 FRAME ENGINE
5.18.1 REGISTERS
5.19 SWITCH CONTROLLER
5.19.1 REGISTERS
6. ABBREVIATIONS
163
164
180
180
180
180
181
225
225
233
233
249
249
267
267
314
Table of Figures
FIGURE 1-1 IOT DEVICE MODE FUCTIONAL BLOCK DIAGRAM .............................................................................................. 8
FIGURE 1-2 IOT GATEWAY MODE FUNCTIONAL BLOCK DIAGRAM ........................................................................................ 8
FIGURE 3-1 MT7688AN DR-QFN PIN DIAGRAM (UP-LEFT VIEW) .................................................................................... 10
FIGURE 3-2 MT7688AN DR-QFN PIN DIAGRAM (DOWN-LEFT VIEW) ............................................................................... 11
FIGURE 3-3 MT7688AN DR-QFN PIN DIAGRAM (DOWN-RIGHT VIEW)............................................................................. 12
FIGURE 3-4 MT7688AN DR-QFN PIN DIAGRAM (UP-RIGHT VIEW) .................................................................................. 13
FIGURE 3-5 MT7688KN DR-QFN PIN DIAGRAM (LEFT VIEW) ......................................................................................... 20
FIGURE 3-6 MT7688KN DR-QFN PIN DIAGRAM (RIGHT SIDE VIEW)................................................................................. 21
FIGURE 4-1 DDR2 SDRAM COMMAND ....................................................................................................................... 35
FIGURE 4-2 DDR2 SDRAM WRITE DATA...................................................................................................................... 35
FIGURE 4-3 DDR2 SDRAM READ DATA ....................................................................................................................... 35
FIGURE 4-4 SPI INTERFACE ......................................................................................................................................... 37
FIGURE-4-5 I2S INTERFACE......................................................................................................................................... 38
FIGURE 4-6 PCM INTERFACE....................................................................................................................................... 39
FIGURE 4-7 POWER ON SEQUENCE .............................................................................................................................. 40
FIGURE 4-8 TOP VIEW................................................................................................................................................ 40
FIGURE 4-9 SIDE VIEW ............................................................................................................................................... 41
FIGURE 4-10 “B” EXPANDED....................................................................................................................................... 41
FIGURE 4-11 BOTTON VIEW ........................................................................................................................................ 42
FIGURE 4-12 TOP VIEW.............................................................................................................................................. 43
FIGURE 4-13 SIDE VIEW ............................................................................................................................................. 44
FIGURE 4-14 “B” EXPANDED....................................................................................................................................... 44
FIGURE 4-15 BOTTOM VIEW ....................................................................................................................................... 45
FIGURE 4-16 MT7688AN TOP MARKING...................................................................................................................... 47
FIGURE 4-17 MT7688KN TOP MARKING...................................................................................................................... 47
FIGURE 4-18 REFLOW PROFILE FOR MT7688 ................................................................................................................ 47
FIGURE 5-1 SYSTEM CONTROL BLOCK DIAGRAM ............................................................................................................. 49
FIGURE 5-2 TIMER BLOCK DIAGRAM............................................................................................................................. 66
FIGURE 5-3 QOS ARBITRATION BLOCK DIAGRAM ............................................................................................................ 95
FIGURE 5-4 PROGRAMMABLE I/O BLOCK DIAGRAM ...................................................................................................... 107
FIGURE 5-5 I2S TRANSMITTER BLOCK DIAGRAM............................................................................................................ 131
FIGURE 5-6 I2S TRANSMIT/RECEIVE ........................................................................................................................... 131
FIGURE 5-7 SPI CONTROLLER BLOCK DIAGRAM ............................................................................................................ 138
FIGURE 5-8 PCM CONTROLLER BLOCK DIAGRAM.......................................................................................................... 162
FIGURE 5-9 GENERIC DMA CONTROLLER BLOCK DIAGRAM............................................................................................. 180
Page 5 of 317
© 2016 MediaTek Inc.
This document contains information that is proprietary to MediaTek Inc. (“MediaTek”) and/or its licensor(s).
Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.
5 Page 
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MediaTek MT7688 Datasheet
3.1.2 Down-left side
I2C_SCLK
I2C_SD
SOC_CO_V12D_1
SOC_IO_V33D_1
SPI_CS1
SPI_CLK
SPI_MISO
SPI_MOSI
SPI_CS0
GPIO0
UART_TXD0
UART_RXD0
AVDD33_TX_P0
MDI_RP_P0
MDI_RN_P0
MDI_TP_P0
MDI_TN_P0
NC1
AVDD33_COM
EPHY_VRT
20
21 DIG
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
EPHY
USB
41 43 45 47 49 51 53 55 57 59 61
40 42 44 46 48 50 52 54 56 58 60 62
Figure 3-2 MT7688AN DR-QFN Pin Diagram (down-left view)
Page 11 of 317
© 2016 MediaTek Inc.
This document contains information that is proprietary to MediaTek Inc. (“MediaTek”) and/or its licensor(s).
Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MT7688.PDF ] | |
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