CAT24C32 Datasheet PDF - ON Semiconductor
| Part Number | CAT24C32 | |
| Description | 32kb I2C CMOS Serial EEPROM | |
| Manufacturers | ON Semiconductor | |
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CAT24C32
32-Kb I2C CMOS Serial
EEPROM
Description
The CAT24C32 is a 32−Kb CMOS Serial EEPROM devices,
internally organized as 4096 words of 8 bits each.
It features a 32−byte page write buffer and supports the Standard
(100 kHz), Fast (400 kHz) and Fast−Plus (1 MHz) I2C protocol.
External address pins make it possible to address up to eight
CAT24C32 devices on the same bus.
Features
• Supports Standard, Fast and Fast−Plus I2C Protocol
• 1.7 V to 5.5 V Supply Voltage Range
• 32−Byte Page Write Buffer
• Hardware Write Protection for Entire Memory
• Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs
(SCL and SDA)
• Low Power CMOS Technology
• 1,000,000 Program/Erase Cycles
• 100 Year Data Retention
• Industrial and Extended Temperature Range
• PDIP, SOIC, TSSOP, UDFN, US 8−lead, WLCSP 4−ball and 5−ball
Packages
• This Device is Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
www.onsemi.com
SOIC−8
W SUFFIX
CASE 751BD
UDFN8
HU4 SUFFIX
CASE 517AZ
US8 *
US SUFFIX
CASE 493
PDIP−8
L SUFFIX
CASE 646AA
TSSOP−8
Y SUFFIX
CASE 948AL
WLCSP5
C5A SUFFIX
CASE 567JQ
WLCSP4
C4C SUFFIX
CASE 567JY
PIN CONFIGURATIONS (Top Views)
12 3
1
VCC
2
VSS A
SCL SDA B
WLCSP4 (C4C)
VCC VSS
SDA
WP SCL
A
B
C
WLCSP5 (C5A)
1
A0
VCC
A1 WP
A2 SCL
VSS SDA
PDIP (L), SOIC (W), TSSOP (Y),
US (US), UDFN (HU4)
For the location of Pin 1, please consult the
corresponding package drawing.
* In Development; please contact factory for availability
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
June, 2015 − Rev. 24
1
Publication Order Number:
CAT24C32/D
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CAT24C32
Power−On Reset (POR)
Each CAT24C32 incorporates Power−On Reset (POR)
circuitry which protects the internal logic against powering
up in the wrong state. The device will power up into Standby
mode after VCC exceeds the POR trigger level and will
power down into Reset mode when VCC drops below the
POR trigger level. This bi−directional POR behavior
protects the device against ‘brown−out’ failure following a
temporary loss of power.
Pin Description
SCL: The Serial Clock input pin accepts the clock signal
generated by the Master.
SDA: The Serial Data I/O pin accepts input data and delivers
output data. In transmit mode, this pin is open drain. Data is
acquired on the positive edge, and is delivered on the
negative edge of SCL.
A0, A1 and A2: The Address inputs set the device address
that must be matched by the corresponding Slave address
bits. The Address inputs are hard−wired HIGH or LOW
allowing for up to eight devices to be used (cascaded) on the
same bus. When left floating, these pins are pulled LOW
internally. The Address inputs are not available for use with
WLCSP 4−ball and 5−ball.
WP: When pulled HIGH, the Write Protect input pin
inhibits all write operations. When left floating, this pin is
pulled LOW internally. The WP input is not available for the
WLCSP 4−ball, therefore all write operations are allowed
for the device in this package.
Functional Description
The CAT24C32 supports the Inter−Integrated Circuit
(I2C) Bus protocol. The protocol relies on the use of a Master
device, which provides the clock and directs bus traffic, and
Slave devices which execute requests. The CAT24C32
operates as a Slave device. Both Master and Slave can transmit
or receive, but only the Master can assign those roles.
I2C Bus Protocol
The 2−wire I2C bus consists of two lines, SCL and SDA,
connected to the VCC supply via pull−up resistors. The
Master provides the clock to the SCL line, and either the
Master or the Slaves drive the SDA line. A ‘0’ is transmitted
by pulling a line LOW and a ‘1’ by letting it stay HIGH. Data
transfer may be initiated only when the bus is not busy (see
A.C. Characteristics). During data transfer, SDA must
remain stable while SCL is HIGH.
START/STOP Condition
An SDA transition while SCL is HIGH creates a START
or STOP condition (Figure 2). The START consists of a
HIGH to LOW SDA transition, while SCL is HIGH. Absent
the START, a Slave will not respond to the Master. The
STOP completes all commands, and consists of a LOW to
HIGH SDA transition, while SCL is HIGH.
Device Addressing
The Master addresses a Slave by creating a START
condition and then broadcasting an 8−bit Slave address. For
the CAT24C32, the first four bits of the Slave address are set
to 1010 (Ah); the next three bits, A2, A1 and A0, must match
the logic state of the similarly named input pins. The devices
in WLCSP (C5A and C4C) respond only to the Slave
Address with A2 A1 A0 = 0 0 0. The R/W bit tells the Slave
whether the Master intends to read (1) or write (0) data
(Figure 3).
Acknowledge
During the 9th clock cycle following every byte sent to the
bus, the transmitter releases the SDA line, allowing the
receiver to respond. The receiver then either acknowledges
(ACK) by pulling SDA LOW, or does not acknowledge
(NoACK) by letting SDA stay HIGH (Figure 4). Bus timing
is illustrated in Figure 5.
SCL
SDA
START
CONDITION
Figure 2. Start/Stop Timing
STOP
CONDITION
1 0 1 0 A2 A1 A0 R/W
DEVICE ADDRESS*
* The devices in WLCSP 4−ball and 5−ball respond only to Slave Address byte with A2 A1 A0 = 0 0 0
Figure 3. Slave Address Bits
www.onsemi.com
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| Information | Total 16 Pages | |
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