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PDF SX1231J Data sheet ( 特性 )

部品番号 SX1231J
部品説明 Low Power Integrated UHF Transceiver
メーカ Semtech Corporation
ロゴ Semtech Corporation ロゴ 

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SX1231J Datasheet, SX1231J PDF,ピン配置, 機能
SX1231J
WIRELESS & SENSING
SX1231J Transceiver
Low Power Integrated UHF Transceiver
DATASHEET
RFIO
VBAT1&2
VR_ANA
VR_DIG
Power Distribution System
LNA
Σ/Δ
Single to
Mixers
Modulators
Differential
RC
Oscillator
GND
VR_PA
PA_BOOST
PA0
Ramp &
Control
PA1&2
Tank
Inductor
Loop
Filter
Division by
2, 4 or 6
Frac-N PLL
Synthesizer
XO
32 MHz
XTAL
RSSI
AFC
GND
RESET
SPI
RXTX
DIO0
DIO1
DIO2
DIO3
DIO4
DIO5
GENERAL DESCRIPTION
The SX1231J is an ARIB compliant highly integrated RF
transceiver which operates over all Japanese sub-GHz
frequency bands. Its highly integrated digital architecture
minimizes external components and provides flexibility for
optimizing the system parameters and performance. The
high sensitivity and exceptional blocking performance
combined with optimized IIP3 maximizes the range in
harshest environments. The industries lowest sleep current,
fastest wake times, and low receive current extend the
battery life for any application. The transmit output power is
programmable up to +17dBm and delivers constant
performance over the battery voltage lifetime. TrueRF™
technology enables a low-cost external component count
(eliminating SAW filter) while still satisfying ARIB, FCC, and
ETSI regulations. The device supports IEEE 15.4d/g
mandatory modes.
APPLICATIONS
Š Smart metering and IEEE15.4d/g
Š Wireless sensor networks
Š Home and building automation
Š Wireless alarm and security systems
Š Industrial monitoring and control
Š Active RFID tags
Š Remote keyless entry (RKE) and automotive
KEY PRODUCT FEATURES
Š High Sensitivity: down to -120 dBm at 1.2 kbps
Š Robust Selectivity: 42dB at 25kHz offset
Š Bullet-proof front end: IIP3 = -18 dBm, IIP2 = +35 dBm,
80 dB Blocking Immunity, no Image Frequency response
Š Low current receive mode = 16 mA
Š Low current sleep mode with register retention =100nA
Š Programmable TX Power: -18 to +17 dBm in 1dB steps
Š Constant RF performance over VDD voltage range
Š FSK bit rates up to 300 kb/s
Š Fully integrated synthesizer with a resolution of 61 Hz
Š FSK, GFSK, MSK, GMSK and OOK modulations
Š Built-in bit synchronizer for clock recovery
Š Incoming sync word recognition
Š 115 dB+ dynamic range RSSI
Š Automatic RF sense with ultra-fast AFC
Š Packet engine with CRC, AES-128, and 66-byte FIFO
Š Built-in temperature sensor and low battery indicator
ORDERING INFORMATION
Part Number Package Delivery MOQ / Multiple
MARKETS
Š Japan: ARIB STD-T67 from 426 to 470 MHz
Š Japan: ARIB STD-T108 from 915 to 930 MHz
SX1231JIMLTRT QFN24
Tape &
Reel
3000 pieces
Š Pb-free, Halogen free, RoHS/WEEE compliant product
Rev 2 - April 2012
Page 1
www.semtech.com

1 Page





SX1231J pdf, ピン配列
SX1231J
WIRELESS & SENSING
DATASHEET
Index of Figures
Page
Figure 1. Block Diagram ................................................................................................................................................ 5
Figure 2. Pin Diagram (not to scale) .............................................................................................................................. 6
Figure 3. Marking Diagram ............................................................................................................................................ 6
Figure 4. SX1231J Evaluation Module Schematics ..................................................................................................... 28
Figure 5. QFN 24 Package Outline Drawing and Land Pattern ................................................................................... 31
Figure 6. Tape & Reel Specification, QFN Package .................................................................................................... 32
Index of Tables
Page
Table 1. SX1231J Pinouts .............................................................................................................................................. 7
Table 2. Absolute Maximum Ratings .............................................................................................................................. 8
Table 3. Operating Range .............................................................................................................................................. 8
Table 4. Power Consumption Specification .................................................................................................................... 9
Table 5. Frequency Synthesizer Specification ................................................................................................................ 9
Table 6. Receiver Specification .................................................................................................................................... 10
Table 7. Transmitter Specification ................................................................................................................................ 11
Table 8. Digital Specification ........................................................................................................................................ 12
Table 9. Registers Summary ........................................................................................................................................ 13
Table 10. Common Configuration Registers ................................................................................................................. 16
Table 11. Transmitter Registers ................................................................................................................................... 19
Table 12. Receiver Registers ....................................................................................................................................... 20
Table 13. IRQ and Pin Mapping Registers ................................................................................................................... 22
Table 14. Packet Engine Registers .............................................................................................................................. 24
Table 15. Temperature Sensor Registers ..................................................................................................................... 27
Table 16. Test Registers .............................................................................................................................................. 27
Table 17. SX1231J Evaluation Module BOM ............................................................................................................... 29
Table 18. Revision History ............................................................................................................................................ 33
Rev 2 - April 2012
Page 3
www.semtech.com


3Pages


SX1231J 電子部品, 半導体
WIRELESS & SENSING
1.2. Pin and Marking Diagram
The following diagram shows the pin arrangement of the SX1231J, top view.
SX1231J
DATASHEET
Figure 2. Pin Diagram (not to scale)
Notes yyww refers to the date code
xxxxxx refers to the lot number
Figure 3. Marking Diagram
Rev 2 - April 2012
Page 6
www.semtech.com

6 Page



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