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74LV08のメーカーはNXP Semiconductorsです、この部品の機能は「Quad 2-input AND gate」です。 |
部品番号 | 74LV08 |
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部品説明 | Quad 2-input AND gate | ||
メーカ | NXP Semiconductors | ||
ロゴ | |||
このページの下部にプレビューと74LV08ダウンロード(pdfファイル)リンクがあります。 Total 13 pages
74LV08
Quad 2-input AND gate
Rev. 03 — 6 April 2009
Product data sheet
1. General description
The 74LV08 is a low-voltage Si-gate CMOS device that is pin and function compatible with
74HC08 and 74HCT08.
The 74LV08 provides a quad 2-input AND function.
2. Features
I Wide operating voltage: 1.0 V to 5.5 V
I Optimized for low voltage applications: 1.0 V to 3.6 V
I Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
I Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C
I Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and
Tamb = 25 °C
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
I Multiple package options
I Specified from −40 °C to +85 °C and from −40 °C to +125 °C
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name
74LV08N
−40 °C to +125 °C DIP14
74LV08D
−40 °C to +125 °C SO14
74LV08DB
−40 °C to +125 °C SSOP14
74LV08PW
−40 °C to +125 °C TSSOP14
Description
plastic dual in-line package; 14 leads (300 mil)
plastic small outline package; 14 leads;
body width 3.9 mm
plastic shrink small outline package; 14 leads;
body width 5.3 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT27-1
SOT108-1
SOT337-1
SOT402-1
1 Page NXP Semiconductors
74LV08
Quad 2-input AND gate
5.2 Pin description
Table 2. Pin description
Symbol
Pin
1A, 2A, 3A, 4A
1, 4, 9, 12
1B, 2B, 3B, 4B
2, 5, 10, 13
1Y, 2Y, 3Y, 4Y
3, 6, 8, 11
GND
7
VCC
14
Description
data input
data input
data output
ground (0 V)
supply voltage
6. Functional description
Table 3.
Input
nA
L
X
H
Function selection[1]
nB
X
L
H
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care
7. Limiting values
Output
nY
L
L
H
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min Max Unit
VCC
IIK
IOK
IO
ICC
IGND
Tstg
Ptot
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
VI < −0.5 V or VI > VCC + 0.5 V
VO < −0.5 V or VO > VCC + 0.5 V
VO = −0.5 V to (VCC + 0.5 V)
Tamb = −40 °C to +125 °C
DIP14 package
−0.5
[1] -
[1] -
-
-
−50
−65
[2]
-
+7.0
±20
±50
±25
50
-
+150
V
mA
mA
mA
mA
mA
°C
750 mW
SO14, SSOP14, TSSOP14
- 500 mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For DIP14 packages: above 70 °C the value of Ptot derates linearly with 12 mW/K.
For SO14 packages: above 70 °C the value of Ptot derates linearly with 8 mW/K.
For (T)SSOP14 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K.
74LV08_3
Product data sheet
Rev. 03 — 6 April 2009
© NXP B.V. 2009. All rights reserved.
3 of 13
3Pages NXP Semiconductors
11. Waveforms
74LV08
Quad 2-input AND gate
VI
nA, nB input
GND
VOH
nY output
VOL
VM
t PHL
VM
t PLH
mna224
Fig 6.
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
The input (nA, nB) to output (nY) propagation delays
Table 8. Measurement points
Supply voltage
VCC
< 2.7 V
2.7 V to 3.6 V
≥ 4.5 V
Input
VM
0.5VCC
1.5 V
0.5VCC
Output
VM
0.5VCC
1.5 V
0.5VCC
VCC
PULSE
GENERATOR
VI
D.U.T.
VO
RT
CL
50 pF
RL
1 kΩ
001aaa663
Fig 7.
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
Load circuit for switching times
Table 9. Test data
Supply voltage
VCC
< 2.7 V
2.7 V to 3.6 V
≥ 4.5 V
Input
VI
VCC
2.7 V
VCC
tr, tf
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
74LV08_3
Product data sheet
Rev. 03 — 6 April 2009
© NXP B.V. 2009. All rights reserved.
6 of 13
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