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KSZ8851-16 の電気的特性と機能

KSZ8851-16のメーカーはMicrel Semiconductorです、この部品の機能は「Single-Port Ethernet MAC Controller」です。


製品の詳細 ( Datasheet PDF )

部品番号 KSZ8851-16
部品説明 Single-Port Ethernet MAC Controller
メーカ Micrel Semiconductor
ロゴ Micrel Semiconductor ロゴ 




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KSZ8851-16 Datasheet, KSZ8851-16 PDF,ピン配置, 機能
KSZ8851-16/32MQL/MQLI
Single-Port Ethernet MAC Controller
with 8/16-Bit or 32-Bit Non-PCI Interface
Rev. 2.0
General Description
The KSZ8851M-series is a single-port controller chip with
a non-PCI CPU interface and is available in 8/16-bit and
32-bit bus designs. This datasheet describes the 128-pin
PQFP KSZ8851-16/32MQL for applications requiring high-
performance from single-port Ethernet Controller with
8/16-bit or 32-bit generic processor interface. The
KSZ8851M offers the most cost-effective solution for
adding high-throughput Ethernet connectivity to traditional
embedded systems.
The KSZ8851M is a single chip, mixed analog/digital
device offering Wake-on-LAN technology for effectively
addressing Fast Ethernet applications. It consists of a Fast
Ethernet MAC controller, an 8-bit, 16-bit and 32-bit generic
host processor interface and incorporates a unique
dynamic memory pointer with 4-byte buffer boundary and
a fully utilizable 18KB for both TX (allocated 6KB) and RX
(allocated 12KB) directions in host buffer interface.
The KSZ8851M is designed to be fully compliant with the
appropriate IEEE 802.3 standards. An industrial
temperature-grade version of the KSZ8851M, the
KSZ8851MQLI is also available (see “Ordering Information
section).
Functional Diagram
LinkMD®
Physical signal transmission and reception are enhanced
through the use of analog circuitry, making the design
more efficient and allowing for lower-power consumption.
The KSZ8851M is designed using a low-power CMOS
process that features a single 3.3V power supply with
options for 1.8V, 2.5V or 3.3V VDD I/O. The device
includes an extensive feature set that offers management
information base (MIB) counters and CPU control/data
interfaces with single bus timing.
The KSZ8851M includes unique cable diagnostics feature
called LinkMD®. This feature determines the length of the
cabling plant and also ascertains if there is an open or
short condition in the cable. Accompanying software
enables the cable length and cable conditions to be
conveniently displayed. In addition, the KSZ8851M
supports Hewlett Packard (HP) Auto-MDIX thereby
eliminating the need to differentiate between straight or
crossover cables in applications.
Figure 1. KSZ8851-16/32MQL/MQLI Functional Diagram
LinkMD is a registered trademark of Micrel, Inc.
Magic Packet is a trademark of Advanced Micro Devices, Inc.
Product names used in this datasheet are for identification purposes
only and may be trademarks of their respective companies.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
August 2009
M9999-083109-2.0

1 Page





KSZ8851-16 pdf, ピン配列
Micrel, Inc.
Ordering Information
Part Number
KSZ8851-16MQL
KSZ8851-32MQL
KSZ8851-16MQLI
KSZ8851-32MQLI
KSZ8851-16MQL-Eval
Temperature Range
0ºC to 70ºC
0ºC to 70ºC
–40ºC to +85ºC
–40ºC to +85ºC
Evaluation Board for the KSZ8851-16MQL
KSZ8851-16/32 MQL/MQLI
Package
128-Pin PQFP
128-Pin PQFP
128-Pin PQFP
128-Pin PQFP
Lead Free
Pb-Free
Pb-Free
Pb-Free
Pb-Free
Revision History
Revision
1.0
1.1
Date
6/30/2008
2/13/2009
2.0 8/31/2009
Summary of Changes
First released Information.
Improved EDS Rating up to 6KV, revised Ordering Information and Updated Table content
and description.
Change revision ID from “0” to “1” in CIDER (0xc0) register. Update pins 24, 38, 43, 57, 63
and 91 description for 1.8V VDD_IO supply.
August 2009
3 M9999-083109-2.0


3Pages


KSZ8851-16 電子部品, 半導体
Micrel, Inc.
KSZ8851-16/32 MQL/MQLI
Wakeup Frame 2 Byte Mask 1 Register (0x56 – 0x57): WF2BM1 ................................................................................ 56
Wakeup Frame 2 Byte Mask 2 Register (0x58 – 0x59): WF2BM2 ................................................................................ 56
Wakeup Frame 2 Byte Mask 3 Register (0x5A – 0x5B): WF2BM3................................................................................ 56
0x5C – 0x5F: Reserved .................................................................................................................................................. 56
Wakeup Frame 3 CRC0 Register (0x60 – 0x61): WF3CRC0 ........................................................................................ 56
Wakeup Frame 3 CRC1 Register (0x62 – 0x63): WF3CRC1 ........................................................................................ 56
Wakeup Frame 3 Byte Mask 0 Register (0x64 – 0x65): WF3BM0 ................................................................................ 56
Wakeup Frame 3 Byte Mask 1 Register (0x66 – 0x67): WF3BM1 ................................................................................ 56
Wakeup Frame 3 Byte Mask 2 Register (0x68 – 0x69): WF3BM2 ................................................................................ 57
Wakeup Frame 3 Byte Mask 3 Register (0x6A – 0x6B): WF3BM3................................................................................ 57
0x6C – 0x6F: Reserved .................................................................................................................................................. 57
Transmit Control Register (0x70 – 0x71): TXCR............................................................................................................ 57
Transmit Status Register (0x72 – 0x73): TXSR ............................................................................................................. 58
Receive Control Register 1 (0x74 – 0x75): RXCR1 ....................................................................................................... 58
Receive Control Register 2 (0x76 – 0x77): RXCR2 ....................................................................................................... 59
TXQ Memory Information Register (0x78 – 0x79): TXMIR ............................................................................................ 60
0x7A – 0x7B: Reserved .................................................................................................................................................. 60
Receive Frame Header Status Register (0x7C – 0x7D): RXFHSR ............................................................................... 60
Receive Frame Header Byte Count Register (0x7E – 0x7F): RXFHBCR...................................................................... 61
TXQ Command Register (0x80 – 0x81): TXQCR .......................................................................................................... 61
RXQ Command Register (0x82 – 0x83): RXQCR.......................................................................................................... 61
TX Frame Data Pointer Register (0x84 – 0x85): TXFDPR............................................................................................. 62
RX Frame Data Pointer Register (0x86 – 0x87): RXFDPR............................................................................................ 63
0x88 – 0x8B: Reserved .................................................................................................................................................. 63
RX Duration Timer Threshold Register (0x8C – 0x8D): RXDTTR ................................................................................. 63
RX Data Byte Count Threshold Register (0x8E – 0x8F): RXDBCTR ............................................................................ 64
Interrupt Enable Register (0x90 – 0x91): IER ................................................................................................................ 64
Interrupt Status Register (0x92 – 0x93): ISR ................................................................................................................. 65
0x94 – 0x9B: Reserved .................................................................................................................................................. 66
RX Frame Count & Threshold Register (0x9C – 0x9D): RXFCTR................................................................................. 66
TX Next Total Frames Size Register (0x9E – 0x9F): TXNTFSR ................................................................................... 66
MAC Address Hash Table Register 0 (0xA0 – 0xA1): MAHTR0.................................................................................... 66
MAC Address Hash Table Register 1 (0xA2 – 0xA3): MAHTR1.................................................................................... 66
MAC Address Hash Table Register 2 (0xA4 – 0xA5): MAHTR2.................................................................................... 67
MAC Address Hash Table Register 3 (0xA6 – 0xA7): MAHTR3.................................................................................... 67
0xA8 – 0xAF: Reserved.................................................................................................................................................. 67
Flow Control Low Watermark Register (0xB0 – 0xB1): FCLWR.................................................................................... 67
Flow Control High Watermark Register (0xB2 – 0xB3): FCHWR................................................................................... 67
Flow Control Overrun Watermark Register (0xB4 – 0xB5): FCOWR............................................................................. 67
0xB6 – 0xBF: Reserved.................................................................................................................................................. 68
Chip ID and Enable Register (0xC0 – 0xC1): CIDER .................................................................................................... 68
0xC2 – 0xC5: Reserved ................................................................................................................................................. 68
Chip Global Control Register (0xC6 – 0xC7): CGCR..................................................................................................... 68
Indirect Access Control Register (0xC8 – 0xC9): IACR ................................................................................................. 68
0xCA – 0xCF: Reserved ................................................................................................................................................. 69
Indirect Access Data Low Register (0xD0 – 0xD1): IADLR............................................................................................ 69
Indirect Access Data High Register (0xD2 – 0xD3): IADHR .......................................................................................... 69
Power Management Event Control Register (0xD4 – 0xD5): PMECR........................................................................... 69
August 2009
6 M9999-083109-2.0

6 Page



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共有リンク

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KSZ8851-16

Single-Port Ethernet MAC Controller

Micrel Semiconductor
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KSZ8851-16MLLI

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KSZ8851-16MLLU

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