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FIN1049のメーカーはFairchild Semiconductorです、この部品の機能は「LVDS Dual Line Driver」です。 |
部品番号 | FIN1049 |
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部品説明 | LVDS Dual Line Driver | ||
メーカ | Fairchild Semiconductor | ||
ロゴ | |||
このページの下部にプレビューとFIN1049ダウンロード(pdfファイル)リンクがあります。 Total 10 pages
March 2003
Revised March 2003
FIN1049
LVDS Dual Line Driver with Dual Line Receiver
General Description
This dual Driver-Receiver is designed for high speed inter-
connects utilizing Low Voltage Differential Signaling
(LVDS) technology. The Driver accepts LVTTL inputs and
translates them to LVDS outputs. The Receiver accepts
LVDS inputs and translates them to LVTTL outputs. The
LVDS levels have a typical differential output swing of
350mV which provide for low EMI at ultra low power dissi-
pation even at high frequencies. The FIN1049 can accept
LVPECL inputs for translating from LVPECL to LVDS. The
En and Enb inputs are ANDed together to enable/disable
the outputs. The enables are common to all four outputs. A
single line driver and single line receiver function is also
available in the FIN1019.
Features
s Greater than 400 Mbps data rate
s 3.3V power supply operation
s Low power dissipation
s Fail safe protection for open-circuit conditions
s Meets or exceeds the TIA/EIA-644-A LVDS standard
s 16-pin TSSOP package saves space
s Flow-through pinout simplifies PCB layout
s Enable/Disable for all outputs
s Industrial operating temperature range:
−40°C to +85°C
Ordering Code:
Order Number Package Number
Package Description
FIN1049MTC
MTC16
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pin Descriptions
Connection Diagram
Pin Name
Description
RIN1+, RIN2+ Non-Inverting LVDS Inputs
RIN1−, RIN2− Inverting LVDS Inputs
DOUT1+, DOUT2+ Non-Inverting Driver Outputs
DOUT1−, DOUT2− Inverting Driver Outputs
EN, ENb Driver Enable Pins for All Outputs
ROUT1, ROUT2
DIN2, DIN2
VCC
GND
LVTTL Output Pins for ROUT1 and ROUT2
LVTTL Input Pins for DIN1 and DIN2
Power Supply (3.3V)
Ground
© 2003 Fairchild Semiconductor Corporation DS500846
www.fairchildsemi.com
1 Page Absolute Maximum Ratings(Note 2)
Supply Voltage (VCC)
LVDS DC Input Voltage (VIN)
LVDS DC Output Voltage (VOUT)
Driver Short Circuit Current (IOSD)
Storage Temperature Range (TSTG)
Max Junction Temperature (TJ)
Lead Temperature (TL)
(Soldering, 10 seconds)
ESD (Human Body Model)
ESD (Machine Model)
−0.5V to +4.6V
−0.5V to +4.6V
−0.5V to +4.6V
Continuous 10mA
−65°C to +150°C
150°C
260°C
>7000V
>250V
Recommended Operating
Conditions
Supply Voltage (VCC)
Magnitude of Differential Voltage
(|VID|)
Operating Temperature (TA)
3.0V to 3.6V
100mV to VCC
−40°C to +85°C
Note 2: The “Absolute Maximum Ratings”: are those values beyond which
damage to the device may occur. The databook specifications should be
met, without exception, to ensure that the system design is reliable over its
power supply, temperature and output/input loading variables. Fairchild
does not recommend operation of circuits outside databook specification.
DC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol
Parameter
Test Conditions
Min Typ
(Note 3)
Max
VTH
VTL
VIC
IIN
VIH
VIL
IIN
VIK
VOD
∆VOD
LVDS Input DC Specifications (RIN1+, RIN1−, RIN2+, RIN2−) See Figure 1 and Table 1
Differential Input Threshold HIGH
Differential Input Threshold LOW
VCM = 1.2V, 0.05V, 2.35V
−100
0.0
0.0
Common Mode Voltage Range
VID = 100mV, VCC = 3.3V
VID/2
Input Current
VCC = 0V or 3.6V, VIN = 0V or 2.8V
CMOS/ LVTTL Input DC Specifications (EN, ENb, DIN1, DIN2)
Input High Voltage (LVTTL)
2.0
Input Low Voltage (LVTTL)
GND
Input Current
(EN, ENb, DIN1, DIN2, RINx+, and
RINx−)
VIN = 0V or VCC
Input Clamp Voltage
VIK = −18mA
−1.5
LVDS Output DC Specifications (DOUT1+, DOUT1−, DOUT2+, DOUT2−)
Output Differential Voltage
250
−0.7
350
VOD Magnitude Change from
Differential LOW-to-HIGH
RL = 100Ω,
Driver Enabled,
35.0
VCC − (VID/2)
±20.0
VCC
0.8
±20.0
450
35.0
VOS
∆VOS
Offset Voltage
Offset Magnitude Change from
Differential LOW-to-HIGH
See Figure 2
1.125
1.25
1.375
25.0
IOS
IOSD
Short Circuit Output Current
DOUT+ = 0V & DOUT− = 0V, Driver Enabled
VOD = 0V, Driver Enabled
−9.0
−9.0
IOFF
Power-Off Input or Output Current
VCC = 0V, VOUT = 0V or VCC
±20.0
IOZD
Disabled Output Leakage Current
Driver Disabled, DOUT+ = 0V or VCC
or DOUT− = 0V or VCC
±10.0
CMOS/LVTTL Output DC Specifications (ROUT1, ROUT2)
VOH Output High Voltage
IOH = −2mA, VID = 200mV
2.7
VOL Output Low Voltage
IOL = 2mA, VID = 200mV
0.250
IOZ
Disabled Output Leakage Current
Driver Disabled, ROUTn = 0V or VCC
±10.0
ICC Power Supply Current (Note 4) Drivers Enabled, Any Valid Input Condition
25.0
ICCZ
Power Supply Current
Drivers Disabled
10.0
CIND
Input Capacitance
LVDS Input
3.0
COUT
Output Capacitance
LVDS Output
4.0
CINT
Input Capacitance
LVTTL Input
3.5
Note 3: All typical values are at TA = 25°C and with VCC = 3.3V.
Note 4: Both driver and receiver inputs are static. All LVDS outputs have 100Ω load. None of the outputs have any lumped capacitive load.
Units
mV
mV
V
mA
V
V
µA
V
mV
mV
V
mV
mA
mA
µA
µA
V
V
µA
mA
mA
pF
pF
pF
3 www.fairchildsemi.com
3Pages Required Specifications (Continued)
Note A: RL = 100Ω
Note B: ZO = 50Ω and CT = 15 pF Distributed
FIGURE 3. LVDS Output Propagation Delay and Transition Time Test Circuit
FIGURE 4. LVTTL Input to LVDS Output AC Waveform
www.fairchildsemi.com
6
6 Page | |||
ページ | 合計 : 10 ページ | ||
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