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SST29LE512 の電気的特性と機能

SST29LE512のメーカーはSSTです、この部品の機能は「512 Kilobit (64K x8) Page-Mode EEPROM」です。


製品の詳細 ( Datasheet PDF )

部品番号 SST29LE512
部品説明 512 Kilobit (64K x8) Page-Mode EEPROM
メーカ SST
ロゴ SST ロゴ 




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SST29LE512 Datasheet, SST29LE512 PDF,ピン配置, 機能
512 Kilobit (64K x8) Page-Mode EEPROM
SST29EE512 / SST29LE512 / SST29VE512
FEATURES:
• Single Voltage Read and Write Operations
– 5.0V-only for SST29EE512
– 3.0-3.6V for SST29LE512
– 2.7-3.6V for SST29VE512
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption
– Active Current: 20 mA (typical) for 5V and
10 mA (typical) for 3.0/2.7V
– Standby Current: 10 µA (typical)
• Fast Page-Write Operation
– 128 Bytes per Page, 512 Pages
– Page-Write Cycle: 5 ms (typical)
– Complete Memory Rewrite: 2.5 sec (typical)
– Effective Byte-Write Cycle
Time: 39 µs (typical)
Data Sheet
• Fast Read Access Time
– 5.0V-only operation: 70 and 90 ns
– 3.0-3.6V operation: 150 and 200 ns
– 2.7-3.6V operation: 200 and 250 ns
• Latched Address and Data
• Automatic Write Timing
– Internal VPP Generation
• End of Write Detection
– Toggle Bit
– Data# Polling
• Hardware and Software Data Protection
• TTL I/O Compatibility
• JEDEC Standard
– Flash EEPROM Pinouts and command sets
• Packages Available
– 32 Pin PDIP
– 32-Pin PLCC
– 32-Pin TSOP (8mm x 14mm, 8mm x 20mm)
PRODUCT DESCRIPTION
The SST29EE512/29LE512/29VE512 are 64K x8
CMOS, Page-Write EEPROMs manufactured with
SST’s proprietary, high performance CMOS
SuperFlash technology. The split-gate cell design and
thick oxide tunneling injector attain better reliability
and manufacturability compared with alternate ap-
proaches. The SST29EE512/29LE512/29VE512 write
with a single power supply. Internal Erase/Program is
transparent to the user. The SST29EE512/29LE512/
29VE512 conform to JEDEC standard pinouts for byte-
wide memories.
Featuring high performance Page-Write, the
SST29EE512/29LE512/29VE512 provide a typical
Byte-Write time of 39 µsec. The entire memory, i.e., 64
KBytes, can be written page-by-page in as little as 2.5
seconds, when using interface features such as
Toggle Bit or Data# Polling to indicate the completion
of a Write cycle. To protect against inadvertent write,
the SST29EE512/29LE512/29VE512 have on-chip
hardware and Software Data Protection schemes.
Designed, manufactured, and tested for a wide spec-
trum of applications, the SST29EE512/29LE512/
29VE512 are offered with a guaranteed Page-Write
endurance of 104 cycles. Data retention is rated at
greater than 100 years.
The SST29EE512/29LE512/29VE512 are suited for ap-
plications that require convenient and economical updat-
ing of program, configuration, or data memory. For all
system applications, the SST29EE512/29LE512/
29VE512 significantly improve performance and reliabil-
ity, while lowering power consumption. The
SST29EE512/29LE512/29VE512 improve flexibility
while lowering the cost for program, data, and configura-
tion storage applications.
To meet high density, surface mount requirements, the
SST29EE512/29LE512/29VE512 are offered in 32-pin
TSOP (8mm x 14mm and 8mm x 20mm) and 32-lead
PLCC packages. A 600-mil, 32-pin PDIP package is also
available. See Figures 1 and 2 for pinouts.
Device Operation
The SST Page-Mode EEPROM offers in-circuit electri-
cal write capability. The SST29EE512/29LE512/
29VE512 do not require separate Erase and Program
operations. The internally timed Write cycle executes
both erase and program transparently to the user. The
SST29EE512/29LE512/29VE512 have industry stan-
dard optional Software Data Protection, which SST
recommends always to be enabled. The SST29EE512/
29LE512/29VE512 are compatible with industry stan-
dard EEPROM pinouts and functionality.
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© 2000 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
301-3 6/00
1
SSF is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.

1 Page





SST29LE512 pdf, ピン配列
512 Kilobit Page-Mode EEPROM
SST29EE512 / SST29LE512 / SST29VE512
The Software Chip-Erase operation is initiated by using a
specific six-byte load sequence. After the load sequence,
the device enters into an internally timed cycle similar to
the Write cycle. During the Erase operation, the only valid
read is Toggle Bit. See Table 4 for the load sequence,
Figure 9 for timing diagram, and Figure 18 for the flow-
chart.
Write Operation Status Detection
The SST29EE512/29LE512/29VE512 provide two soft-
ware means to detect the completion of a Write cycle, in
order to optimize the system write cycle time. The
software detection includes two status bits: Data# Polling
(DQ7) and Toggle Bit (DQ6). The end of write detection
mode is enabled after the rising WE# or CE# whichever
occurs first, which initiates the internal Write cycle.
The actual completion of the nonvolatile write is asyn-
chronous with the system; therefore, either a Data#
Polling or Toggle Bit read may be simultaneous with the
completion of the Write cycle. If this occurs, the system
may possibly get an erroneous result, i.e., valid data may
appear to conflict with either DQ7 or DQ6. In order to
prevent spurious rejection, if an erroneous result occurs,
the software routine should include a loop to read the
accessed location an additional two (2) times. If both
reads are valid, then the device has completed the Write
cycle, otherwise the rejection is valid.
Data# Polling (DQ7)
When the SST29EE512/29LE512/29VE512 are in the
internal Write cycle, any attempt to read DQ7 of the last
byte loaded during the byte-load cycle will receive the
complement of the true data. Once the Write cycle is
completed, DQ7 will show true data. The device is then
ready for the next operation. See Figure 6 for Data#
Polling timing diagram and Figure 15 for a flowchart.
Toggle Bit (DQ6)
During the internal Write cycle, any consecutive attempts
to read DQ6 will produce alternating 0’s and 1’s, i.e.,
toggling between 0 and 1. When the Write cycle is
completed, the toggling will stop. The device is then
ready for the next operation. See Figure 7 for Toggle Bit
timing diagram and Figure 15 for a flowchart. The initial
read of the Toggle Bit will typically be a “1”.
Data Protection
The SST29EE512/29LE512/29VE512 provide both hard-
ware and software features to protect nonvolatile data
from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than
5 ns will not initiate a Write cycle.
VCC Power Up/Down Detection: The Write operation is
inhibited when VCC is less than 2.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inad-
vertent writes during power-up or power-down.
Software Data Protection (SDP)
The SST29EE512/29LE512/29VE512 provide the
JEDEC approved optional Software Data Protection
scheme for all data alteration operations, i.e., Write and
Chip-Erase. With this scheme, any Write operation re-
quires the inclusion of a series of three byte-load opera-
tions to precede the data loading operation. The three
byte-load sequence is used to initiate the Write cycle,
providing optimal protection from inadvertent write opera-
tions, e.g., during the system power-up or power-down.
The SST29EE512/29LE512/29VE512 are shipped with
the Software Data Protection disabled.
The software protection scheme can be enabled by
applying a three-byte sequence to the device, during a
page-load cycle (Figures 4 and 5). The device will then
be automatically set into the data protect mode. Any
subsequent write operation will require the preceding
three-byte sequence. See Table 4 for the specific soft-
ware command codes and Figures 4 and 5 for the timing
diagrams. To set the device into the unprotected mode,
a six-byte sequence is required. See Table 4 for the
specific codes and Figure 8 for the timing diagram. If a
write is attempted while SDP is enabled the device will be
in a non-accessible state for ~ 300 µs. SST recommends
Software Data Protection always be enabled. See Figure
16 for flowcharts.
The SST29EE512/29LE512/29VE512 Software Data
Protection is a global command, protecting (or
unprotecting) all pages in the entire memory array once
enabled (or disabled). Therefore using SDP for a single
Page-Write will enable SDP for the entire array. Single
pages by themselves cannot be SDP enabled or dis-
abled, although the page addressed during the SDP
write will be written.
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© 2000 Silicon Storage Technology, Inc.
3
301-3 6/00


3Pages


SST29LE512 電子部品, 半導体
512 Kilobit Page-Mode EEPROM
SST29EE512 / SST29LE512 / SST29VE512
TABLE 3: OPERATION MODES SELECTION
Mode
CE# OE#
Read
VIL VIL
Page-Write
VIL VIH
Standby
VIH X
Write Inhibit
X VIL
Write Inhibit
XX
Software Chip-Erase VIL
VIH
Product Identification
Hardware Mode
VIL
VIL
Software Mode
VIL VIH
SDP Enable Mode
VIL VIH
SDP Disable Mode VIL VIH
WE#
VIH
VIL
X
X
VIH
VIL
VIH
VIL
VIL
VIL
DQ
DOUT
DIN
High Z
High Z/ DOUT
High Z/ DOUT
DIN
Manufacturer ID (BF)
Device ID (see notes)
Address
AIN
AIN
X
X
X
AIN, See Table 4
A15 - A1 = VIL, A9 = VH, A0 = VIL
A15 - A1 = VIL, A9 = VH, A0= VIH
See Table 4
See Table 4
See Table 4
301 PGM T3.0
TABLE 4: SOFTWARE COMMAND CODES
Command
Sequence
Software Data
Protect Enable
& Page-Write
Software Data
Protect Disable
Software Chip-
Erase
Software ID Entry
1st Bus
Write Cycle
Addr(1) Data
5555H AAH
5555H AAH
5555H AAH
5555H AAH
2nd Bus
Write Cycle
Addr(1) Data
2AAAH 55H
2AAAH 55H
2AAAH 55H
2AAAH 55H
3rd Bus
Write Cycle
Addr(1) Data
5555H A0H
4th Bus
Write Cycle
Addr(1) Data
Addr(2) Data
5555H 80H 5555H AAH
5555H 80H 5555H AAH
5555H 90H
5th Bus
6th Bus
Write Cycle Write Cycle
Addr(1) Data Addr(1) Data
2AAAH 55H 5555H 20H
2AAAH 55H 5555H 10H
Software ID Exit 5555H AAH 2AAAH 55H 5555H F0H
Alternate Software 5555H AAH 2AAAH 55H
ID Entry(3)
5555H 80H 5555H AAH 2AAAH 55H
Notes:
(1) Address format A14-A0 (Hex), Address A15 is a “Don’t Care”.
(2) Page-Write consists of loading up to 128 Bytes (A6 - A0).
(3) Alternate six-byte Software Product ID Command Code
(4) The software Chip-Erase function is not supported by the industrial temperature part.
Please contact SST if you require this function for an industrial temperature part.
Notes for Software Product ID Command Code:
1. With A14 -A1 =0; SST Manufacturer ID = BFH, is read with A0 = 0,
SST29EE512 Device ID = 5DH, is read with A0 = 1,
SST29LE512/29VE512 Device ID = 3DH, is read with A0 = 1.
2. The device does not remain in Software Product ID Mode if powered down.
3. This product supports both the JEDEC standard three-byte command code sequence and
SST’s original six-byte command code sequence. For new designs, SST recommends that
the three-byte command code sequence be used.
5555H 60H
301 PGM T4.0
© 2000 Silicon Storage Technology, Inc.
6
301-3 6/00

6 Page



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部品番号部品説明メーカ
SST29LE512

512 Kilobit (64K x8) Page-Mode EEPROM

SST
SST


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