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ADSP-21488 の電気的特性と機能

ADSP-21488のメーカーはAnalog Devicesです、この部品の機能は「SHARC Processor」です。


製品の詳細 ( Datasheet PDF )

部品番号 ADSP-21488
部品説明 SHARC Processor
メーカ Analog Devices
ロゴ Analog Devices ロゴ 




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ADSP-21488 Datasheet, ADSP-21488 PDF,ピン配置, 機能
SHARC Processor
ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
SUMMARY
High performance 32-bit/40-bit floating-point processor
optimized for high performance audio processing
Single-instruction, multiple-data (SIMD) computational
architecture
On-chip memory—5 Mbits on-chip RAM, 4 Mbits on-chip
ROM
Up to 450 MHz operating frequency
Code compatible with all other members of the SHARC family
The ADSP-2148x processors are available with unique audio-
centric peripherals, such as the digital applications
interface, serial ports, precision clock generators, S/PDIF
transceiver, asynchronous sample rate converters, input
data port, and more
For complete ordering information, see Ordering Guide on
Page 66
Qualified for automotive applications
SIMD Core
Instruction
Cache
5 Stage
Sequencer
DAG1/2
Core
Timer
PEx PEy
FLAGx/IRQx/
TMREXP
JTAG THERMAL
DIODE
Block 0
RAM/ROM
Internal Memory
Block 1
RAM/ROM
Block 2
RAM
Block 3
RAM
DMD
64-BIT
S
DMD
64-BIT
Core Bus
PMD
64-BIT
Cross Bar
PMD 64-BIT
EPD BUS 64-BIT
PERIPHERAL BUS
32-BIT
B0D
64-BIT
B1D
64-BIT
B2D
64-BIT
Internal Memory I/F
IOD0 32-BIT
B3D
64-BIT
IOD1
32-BIT
PERIPHERAL BUS
CORE
FLAGS/
PWM3-1
PCG
C-D
TIMER
1-0
TWI
SPI/B UART
IOD0 BUS
S/PDIF PCG
Tx/Rx A-D
ASRC PDAP/ SPORT
3-0 IDP 7-0
7-0
FFT
FIR
IIR
DTCP/
MTM
SPEP BUS
CORE PWM
WDT FLAGS 3-0
EP
AMI
SDRAM
CTL
DPI Routing/Pins
DPI Peripherals
DAI Routing/Pins
DAI Peripherals
Figure 1. Functional Block Diagram
External Port Pin MUX
Peripherals
External
Port
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
©2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com

1 Page





ADSP-21488 pdf, ピン配列
ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
GENERAL DESCRIPTION
The ADSP-2148x SHARC® processors are members of the
SIMD SHARC family of DSPs that feature Analog Devices’
Super Harvard Architecture. The processors are source code
compatible with the ADSP-2126x, ADSP-2136x, ADSP-2137x,
ADSP-2146x, ADSP-2147x and ADSP-2116x DSPs, as well as
with first generation ADSP-2106x SHARC processors in SISD
(single-instruction, single-data) mode. The ADSP-2148x pro-
cessors are 32-bit/40-bit floating point processors optimized for
high performance audio applications with large on-chip SRAM,
multiple internal buses to eliminate I/O bottlenecks, and an
innovative digital applications interface (DAI).
Table 1 shows performance benchmarks for the ADSP-2148x
processors. Table 2 shows the features of the individual product
offerings.
Table 1. Processor Benchmarks
Benchmark Algorithm
Speed
(at 400 MHz)
1024 Point Complex FFT
(Radix 4, with Reversal)
FIR Filter (per Tap)1
IIR Filter (per Biquad)1
23 μs
1.25 ns
5 ns
Matrix Multiply (Pipelined)
[3 × 3] × [3 × 1]
[4 × 4] × [4 × 1]
11.25 ns
20 ns
Divide (y/×)
7.5 ns
Inverse Square Root
11.25 ns
1 Assumes two files in multichannel SIMD mode
Speed
(at 450 MHz)
20.44 μs
1.1 ns
4.43 ns
10.0 ns
17.78 ns
6.67 ns
10.0 ns
Table 2. ADSP-2148x Family Features
Feature
ADSP-21483 ADSP-21486 ADSP-21487 ADSP-21488 ADSP-21489
Maximum Instruction Rate
RAM
400 MHz
3 Mbits
400 MHz
450 MHz
5 Mbits
400 MHz
2/3 Mbits1
450 MHz
5 Mbits
ROM
Audio Decoders in ROM2
4 Mbits
Yes
No
No
Pulse-Width Modulation
4 Units (3 Units on 100-Lead Packages)
DTCP Hardware Accelerator
External Port Interface (SDRAM, AMI)3
Yes (16-bit)
Contact Analog Devices
AMI Only
Yes (16-bit)
Serial Ports
8
Direct DMA from SPORTs to External Port
(External Memory)
Yes
FIR, IIR, FFT Accelerator
Yes
Watchdog Timer
Yes (176-Lead Package Only)
MediaLB Interface
Automotive Models Only
IDP/PDAP
Yes
UART
1
DAI (SRU)/DPI (SRU2)
Yes
S/PDIF Transceiver
Yes
SPI Yes
TWI
SRC Performance4
1
–128 dB
Thermal Diode
Yes
VISA Support
Package3
176-Lead LQFP EPAD
100-Lead LQFP EPAD
Yes
176-Lead LQFP
EPAD
176-Lead LQFP EPAD
100-Lead LQFP EPAD5
1 See Ordering Guide on Page 66.
2 ROM is factory programmed with latest multichannel audio decoding and post-processing algorithms from Dolby® Labs and DTS®. Decoder/post-processor algorithm
combination support varies depending upon the chip version and the system configurations. Please visit www.analog.com for complete information.
3 The 100-lead packages do not contain an external port. The SDRAM controller pins must be disabled when using this package. For more information, see Pin Function
Descriptions on Page 14. The ADSP-21486 processor in the 176-lead package also does not contain a SDRAM controller. For more information, see 176-Lead LQFP_EP
Lead Assignment on page 60.
4 Some models have –140 dB performance. For more information, see Ordering Guide on page 66.
5 Only available up to 400 MHz. See Ordering Guide on Page 66 for details.
Rev. C | Page 3 of 68 | June 2015


3Pages


ADSP-21488 電子部品, 半導体
ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
subtract in both processing elements while branching and fetch-
ing up to four 32-bit values from memory, all in a single
instruction.
Variable Instruction Set Architecture (VISA)
In addition to supporting the standard 48-bit instructions from
previous SHARC processors, the ADSP-2148x supports new
instructions of 16 and 32 bits. This feature, called Variable
Instruction Set Architecture (VISA), drops redundant/unused
bits within the 48-bit instruction to create more efficient and
compact code. The program sequencer supports fetching these
16-bit and 32-bit instructions from both internal and external
SDRAM memory. This support is not extended to the
asynchronous memory interface (AMI). Source modules need
to be built using the VISA option, in order to allow code genera-
tion tools to create these more efficient opcodes.
On-Chip Memory
The ADSP-21483 and the ADSP-21488 processors contain
3 Mbits of internal RAM (Table 3) and the ADSP-21486,
ADSP-21487, and ADSP-21489 processors contain 5 Mbits of
internal RAM (Table 4). Each memory block supports single-
cycle, independent accesses by the core processor and I/O
processor.
Table 3. Internal Memory Space (3 MBits—ADSP-21483/ADSP-21488)1
IOP Registers 0x0000 0000–0x0003 FFFF
Long Word (64 Bits)
Extended Precision Normal or
Instruction Word (48 Bits)
Normal Word (32 Bits)
Short Word (16 Bits)
Block 0 ROM (Reserved)
0x0004 0000–0x0004 7FFF
Block 0 ROM (Reserved)
0x0008 0000–0x0008 AAA9
Block 0 ROM (Reserved)
0x0008 0000–0x0008 FFFF
Block 0 ROM (Reserved)
0x0010 0000–0x0011 FFFF
Reserved
0x0004 8000–0x0004 8FFF
Reserved
0x0008 AAAA–0x0008 BFFF
Reserved
0x0009 0000–0x0009 1FFF
Reserved
0x0012 0000–0x0012 3FFF
Block 0 SRAM
0x0004 9000–0x0004 CFFF
Block 0 SRAM
0x0008 C000–0x0009 1554
Block 0 SRAM
0x0009 2000–0x0009 9FFF
Block 0 SRAM
0x0012 4000–0x0013 3FFF
Reserved
0x0004 D000–0x0004 FFFF
Reserved
0x0009 1555–0x0009 FFFF
Reserved
0x0009 A000–0x0009 FFFF
Reserved
0x0013 4000–0x0013 FFFF
Block 1 ROM (Reserved)
0x0005 0000–0x0005 7FFF
Block 1 ROM (Reserved)
0x000A 0000–0x000A AAA9
Block 1 ROM (Reserved)
0x000A 0000–0x000A FFFF
Block 1 ROM (Reserved)
0x0014 0000–0x0015 FFFF
Reserved
0x0005 8000–0x0005 8FFF
Reserved
0x000A AAAA–0x000A BFFF
Reserved
0x000B 0000–0x000B 1FFF
Reserved
0x0016 0000–0x0016 3FFF
Block 1 SRAM
0x0005 9000–0x0005 CFFF
Block 1 SRAM
0x000A C000–0x000B 1554
Block 1 SRAM
0x000B 2000–0x000B 9FFF
Block 1 SRAM
0x0016 4000–0x0017 3FFF
Reserved
0x0005 D000–0x0005 FFFF
Reserved
0x000B 1555–0x000B FFFF
Reserved
0x000B A000–0x000B FFFF
Reserved
0x0017 4000–0x0017 FFFF
Block 2 SRAM
0x0006 0000–0x0006 1FFF
Block 2 SRAM
0x000C 0000–0x000C 2AA9
Block 2 SRAM
0x000C 0000–0x000C 3FFF
Block 2 SRAM
0x0018 0000–0x0018 7FFF
Reserved
0x0006 2000– 0x0006 FFFF
Reserved
0x000C 2AAA–0x000D FFFF
Reserved
0x000C 4000–0x000D FFFF
Reserved
0x0018 8000–0x001B FFFF
Block 3 SRAM
0x0007 0000–0x0007 1FFF
Block 3 SRAM
0x000E 0000–0x000E 2AA9
Block 3 SRAM
0x000E 0000–0x000E 3FFF
Block 3 SRAM
0x001C 0000–0x001C 7FFF
Reserved
0x0007 2000–0x0007 FFFF
Reserved
0x000E 2AAA–0x000F FFFF
Reserved
0x000E 4000–0x000F FFFF
Reserved
0x001C 8000–0x001F FFFF
1 Some ADSP-2148x processors include a customer-definable ROM block. ROM addresses on these models are not reserved as shown in this table. Please contact your Analog
Devices sales representative for additional details.
The processor’s SRAM can be configured as a maximum of
160k words of 32-bit data, 320k words of 16-bit data, 106.7k
words of 48-bit instructions (or 40-bit data), or combinations of
different word sizes up to 5 megabits. All of the memory can be
accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit
floating-point storage format is supported that effectively dou-
bles the amount of data that may be stored on-chip. Conversion
between the 32-bit floating-point and 16-bit floating-point
formats is performed in a single instruction. While each mem-
ory block can store combinations of code and data, accesses are
most efficient when one block stores data using the DM bus for
transfers, and the other block stores instructions and data using
the PM bus for transfers.
Using the DM bus and PM buses, with one bus dedicated to a
memory block, assures single-cycle execution with two data
transfers. In this case, the instruction must be available in the
cache.
The memory maps in Table 3 and Table 4 display the internal
memory address space of the processors. The 48-bit space sec-
tion describes what this address range looks like to an
Rev. C | Page 6 of 68 | June 2015

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共有リンク

Link :


部品番号部品説明メーカ
ADSP-21483

SHARC Processor

Analog Devices
Analog Devices
ADSP-21486

SHARC Processor

Analog Devices
Analog Devices
ADSP-21487

SHARC Processor

Analog Devices
Analog Devices
ADSP-21488

SHARC Processor

Analog Devices
Analog Devices


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