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HCPL2200 PDF Datasheet ( 特性, スペック, ピン接続図 )

部品番号 HCPL2200
部品説明 Low Input Current Logic Gate Optocouplers
メーカ Avago
ロゴ Avago ロゴ 



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HCPL2200 Datasheet, HCPL2200 PDF,ピン配置, 機能
HCPL-2200, HCPL-2219
Low Input Current Logic Gate Optocouplers
Data Sheet
Description
The HCPL-2200/2219 are optically coupled logic gates
that combine a GaAsP LED and an integrated high gain
photo detector. The detector has a three state output
stage and has a detector threshold with hysteresis. The
three state output eliminates the need for a pullup
resistor and allows for direct drive of data busses. The
hysteresis provides differential mode noise immunity
and eliminates the potential for output signal chatter.
Asuperiorinternalshieldon theHCPL-2219guarantees
common mode transient immunity of 2.5 kV/µs at a
common mode voltage of 400 volts.
The Electrical and Switching Characteristics of the
HCPL-2200/2219 are guaranteed over the tempera-
ture range of 0° C to 85° C and a VCC range of 4.5 volts to
20 volts. Low IF and wide VCC range allow compatibility
with TTL, LSTTL, and CMOS logic and result in lower
power consumption compared to other high speed
optocouplers. Logic signals are transmitted with a
typical propagation delay of 160 nsec.
The HCPL-2200/2219 are useful for isolating high
speed logic interfaces, buffering of input and output
lines, and implementing isolated line receivers in
high noise environments.
Functional Diagram
Features
• 2.5 kV/µs minimum Common Mode Rejection (CMR) at
VCM = 400 V (HCPL-2219)
• Compatible with LSTTL, TTL, and CMOS logic
• Wide VCC range (4.5 to 20 V)
• 2.5 Mbd guaranteed over temperature
• Low input current (1.6 mA)
• Three state output (no pullup resistor required)
• Guaranteed performance from 0°C to 85°C
• Hysteresis
• Safety approval
– UL recognized -3750 V rms for 1 minute
– CSA approved
– IEC/EN/DIN EN 60747-5-2 approved with
VIORM = 630 V peak (HCPL-2219 Option 060 only)
• MIL-PRF-38534 hermetic version available
(HCPL-5200/1)
Applications
• Isolation of high speed logic systems
• Computer-peripheral interfaces
• Microprocessor system interfaces
• Ground loop elimination
• Pulse transformer replacement
• Isolated buss driver
• High speed line receiver
NC 1
ANODE 2
CATHODE 3
NC 4
SHIELD
8 VCC
7 VO
6 VE
5 GND
TRUTH TABLE
(POSITIVE LOGIC)
LED ENABLE OUTPUT
ON
OFF
ON
OFF
H
H
L
L
Z
Z
H
L
A 0.1 µF bypass capacitor must be connected between pins 5 and 8.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this
component to prevent damage and/or degradation which may be induced by ESD.

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