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PDF ES1373 Data sheet ( Hoja de datos )
| Número de pieza | ES1373 | |
| Descripción | ENSONIQ AudioPCI 97 digital controller | |
| Fabricantes | ETC | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ES1373 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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ENSONIQ AudioPCI™ 97
ES1373
Specification
PRELIMINARY
1. INTRODUCTION
AudioPCI 97 is the new ENSONIQ AC97 digital controller which provides the next
generation of audio performance to the PC market. AudioPCI 97 is a 5.0 Volt PCI bus
compatible device that enables the ENSONIQ SoundScape PCI solution. AudioPCI 97
along with an AC97 CODEC offer the next generation of audio performance in a PC while
maintaining full legacy compatibility without old ISA bus solutions. Some of the
capabilities of AudioPCI 97 are:
• SoundScape WaveTable synthesizer .
• Full DOS Game Compatibility
• Multiple sample rate support
• PCI Bus Master for fast DMA
• Sounds are stored in Main memory.
• Access to Ensoniq’s World Famous Sound Library of over 4000 Sounds
• 3 Stereo inputs and 3 mono inputs can be mixed into the output stream.
• Direct I/O space access of the control registers.
• 100 Pin PQFP {rectangular}
• Digital I/O compatible with consumer mode S/PDIF (out) or I2S (in)
• No ISA bus pins required
• Fully Compliant with PC97 Power Management specification
1 page  
4.7. Joystick
This block contains the logic required to implement the joystick interface for AudioPCI 97.
4.8. UART
This block includes both the transmitter and receiver for the AudioPCI 97 MIDI interface. The UART
controller also implements an eight byte FIFO in the internal memory. This FIFO is then accessed
through the HOST interface block.
4.9. Sample Rate Converter
This block receives or sends samples from/to the serial interface block for the playback/record channels.
The Sample Rate converter block converts two variable input rate playback channels to one fixed rate
(48Khz) output channel. It also takes one fixed input rate (48Khz) record channel and converts it to a
variable rate output channel. The channels are programmed by writing several ram locations that are a
function of the input and output rates. The Sample Rate Converter block has it’s own memory section.
The Sample Rate Converter memory is accessible only by the Sample Rate Converter block.
The first stage consists of expanding the number of input samples by an integer number (N), up to a
maximum of 16, and filling in between the samples with zeros. Then the new samples are filtered by a
long 1/32 band FIR filter. In practice, the zeros are not multiplied with their corresponding FIR
coefficients. The input samples are fed into an input FIFO and the hardware figures out which FIR
coefficient corresponds to each FIFO sample. The starting coefficient and the spacing between successive
coefficients are calculated by aligning the FIR filter with a virtual FIFO which is the expanded version of
the real FIFO.
The coefficient positions also depend on the third stage in the block diagram, the linear interpolator. This
interpolator uses frequency and accumulator registers to interpolate between 2 samples.
4.10. Memory Bus
This pathway is used exclusively to transfer data between the internal sound cache memory and the
various sub-systems. The access priority for this bus is (highest to lowest):
Cache Control block
Host Interface
UART Interface
Serial Interface
4.11. Internal Memory
There are two separate sections of memory in AudioPCI 97. One section is allocated as a cache for the
playback and record channels and also as a FIFO for the UART. The other section is allocated to the
Sample Rate Converter module and is used as a cache for sample rate conversion and also as control
register space for the playback and record channels in the sample rate converter.
The internal memory for the sound cache in AudioPCI 97 is organized as 4 blocks of 64 bytes each. Each
block is divided into 4 pages of 16 bytes each (4 longwords). Memory can be accessed as longwords only.
In order to access a specific page of memory the memory page register must first be setup for the specific
page to be accessed. The first three blocks of memory contain the 3 circular buffers for the 2 playback
channels and the record channel. The last block contains the frame information for the playback and
record channels and also includes the UART FIFO. The memory block and page organization is shown
below :
5 Page 
31:0 R Not implemented
Cardbus CIS Pointer
Addressable as long word
Power on reset value 00000000H
Bit(s) R/W Name
31:0 R Not implemented
00000000H
Data Value
00000000H
Address 28H
Configuration Space
Subsystem Vendor ID
Address 2CH
Addressable as word
Power on reset value 1274H
Configuration Space
Bit(s) R/W Name
Data Value
15:0 R SUBSYSTEM VENDOR ID 1274H
W SUBSYSTEM VENDOR ID Can be written only if SubsysID register (40h) is set
to EAh.
Subsystem ID
Addressable as word
Power on reset value 1371H
Bit(s) R/W Name
15:0 R SUBSYSTEM ID
W SUBSYSTEM ID
Address 2EH
Configuration Space
Data Value
1371H
Can be written only if SubsysID register (40h) is set to EAh.
Expansion ROM Address
Addressable as long word
Power on reset value 00000000H
Bit(s) R/W Name
31:0 R EXP ROM ADDR
Data Value
00000000H
Address 30H
Configuration Space
Capabilities Pointer
Addressable as long word
Power on reset value DCH
Bit(s) R/W Name
7:0 R CAP_PTR
space
Address 34H
Configuration Space
Data Value
DCH - Pointer to first entry of capabilities list in configuration
Interrupt Line
Addressable as byte
Power on reset value xxH
Bit(s) R/W Name
7:0 R/W INTERRUPT
Data Value
Variable
Address 3CH
Configuration Space
Interrupt Pin
Addressable as byte
Power on reset value 01H
Bit(s) R/W Name
7:0 R INTERRUPT PIN
Data Value
01H
Address 3DH
Configuration Space
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ES1373.PDF ] | |
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