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NTP3000 の電気的特性と機能

NTP3000のメーカーはNeoFidelityです、この部品の機能は「2.1 CHANNEL FULL DIGITAL AMPLIFIER」です。


製品の詳細 ( Datasheet PDF )

部品番号 NTP3000
部品説明 2.1 CHANNEL FULL DIGITAL AMPLIFIER
メーカ NeoFidelity
ロゴ NeoFidelity ロゴ 




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NTP3000 Datasheet, NTP3000 PDF,ピン配置, 機能
Power Integrated Processor for Digital Amplifier
NTP3000
NTP3000 1CHIP 2.1CHANNELFULLDIGITALAMPLIFIER
Features
Stereo (30W 2)
2.1 channel (15W2 + 30W)
Wide Supply Voltage Range
(7V~30V)
Floating Point Operation
18 Programmable Biquad Filters
Speaker Compensation
DC cut, LPF, HPF
Parametric Equalizer
PWM Output for External Subwoofer
3D Surround
7 Band Graphic Equalizer
100 dB Dynamic Range
Adaptive Loudness Compensator
based on Psycho Acoustics
Applications
Plasma TV, LCD TV
Docking Station
Mini-Component Audio
Description
NTP3000 is a single chip full digital audio
amplifier including power stage for stereo or
2.1 channel amplifier system. NTP3000 is
integrated with versatile digital audio signal
processing functions, high-fidelity fully digital
PWM modulator and two high-power full bridge
MOSFET stages.
NTP3000 receives 2-channel serial audio data
with sampling frequency from 8 kHz to 192
kHz. It delivers 2x30W in stereo mode or
2x15W + 1x30W in 2.1 channel mode without
heat sink.
Combining use of built-in mixer and biquad
filters can make additional preprocessing like
bass management, loudness control, loud-
speaker response compensation and preset
parametric equalizers possible.
All the functions of NTP3000 are set by I2C
register configuration.
Package
56 pin MLF 8mm by 8mm
BST1A
VDR1A
/RESET
AD
VSS_IO
CLK_I
CLK_O
VDD_IO
DGNDPLL
AGNDPLL
LFM
AVDDPLL
DVDDPLL
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
NTP3000
42 NC
41 VDR2A
40 BST2A
39 PGND2A
38 PGND2A
37 OUT2A
36 OUT2A
35 PVDD2A
34 PVDD2A
33 PVDD2B
32 PVDD2B
31 OUT2B
30 OUT2B
29 PGND2B
Figure 1 NTP3000 Pin Assignment
NeoFidelity, Inc. #1009, Ace Twin Tower 2, 212-30, Guro-dong, Guro-gu, Seoul 152-766 Korea, Phone +82-2-6675-
1100, Fax +82-2-6675-1109, Email [email protected], Web www.neofidelity.com
Copyright © NeoFidelity, Inc. 2005 All rights Reserved. June, 2005
Disclaimer
NeoFidelity, Inc. reserves the right to make changes without notice in the product described in this datasheet
Copyright © NeoFidelity, Inc. 2005
1
Preliminary datasheet – NeoFidelity reserves the right to change specifications at any time without prior notice
R0.73-11.2006

1 Page





NTP3000 pdf, ピン配列
Power Integrated Processor for Digital Amplifier
1. BLOCK DIAGRAM
NTP3000
Figure 2 NTP3000 Block Diagram
2. PIN DESCRIPTIONS
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28, 29
NAME
BST1A
VDR1A
/RESET
AD
VSS_IO
CLK_I
CLK_O
VDD_IO
DGNDPLL
AGNDPLL
LFM
AVDDPLL
DVDDPLL
VSS
DVSS
DVDD
SDATA2)
WCK2)
BCK2)
SDA2)
SCL2)
PWM_SWB
PWM_SWA
PROTECT
FAULT
VDR2B
BST2B
PGND2B
TYPE1)
P
P
I
I
-
I
O
P
-
-
I
P
P
-
-
P
I
I/O
I/O
I/O
I
O
O
O
I
P
P
-
DESCRIPTION
Bootstrap supply, external capacitor to OUT1A is required
Gate drive voltage regulator decoupling pin, capacitor to GND
Active Low to reset NTP3000, Schmitt trigger input
I2C device Address selection
Ground
System master clock input
System master clock output
voltage supply for I/O, 3.3V
Ground
Ground
External loop filter
voltage supply for PLL analog circuit, 1.8V
voltage supply for PLL digital circuit, 1.8V
Ground
Ground
voltage supply for core logic, 1.8V
I2S serial data input
I2S word clock
I2S bit clock
I2C data
I2C clock
PWM output for external subwoofer, negative
PWM output for external subwoofer, positive
External power stage on/off control to protect
input from external power stage
Gate drive voltage regulator decoupling pin, capacitor to GND
Bootstrap supply, external capacitor to OUT1A is required
Ground
Copyright © NeoFidelity, Inc. 2005
Preliminary datasheet – NeoFidelity reserves the right to change specifications at any time without prior notice
3
R0.73-11.2006


3Pages


NTP3000 電子部品, 半導体
Power Integrated Processor for Digital Amplifier
NTP3000
4.1. Start Condition and Stop Condition
I2C bus of NTP3000 is composed of serial clock line (SCL) and serial data line (SDA). SDA can be
changed only when SCL is in low state with exceptions of start condition or stop condition. START
condition means that master is to start transferring data to slave. To make START condition, transit SDA
state from high to low when SCL is high. STOP condition means that master is to finish transferring data
to slave. To make STOP condition, transit SDA state from low to high when SCL is high.
acklowedgement
Slave address
signal from NTP-3000
RA
A
SDA
010 1 01 0
MSB LSB
MSB
SCL
12
S
or
Sr
START or
3
LSB W
456789
1
byte complete
2-8
A
9
Sr
or
P
STOP or
repeated START
repeated START
condition
condition
Figure 4 START Condition and STOP Condition
4.2. I2C Address
The I2C Address of NTP3000 is composed of 7-bit except for Acknowledge bit with 7th bit depending on
AD pin input (Table 1). If AD is low or pulled down, the Address is 0x54 and if AD is high or pulled up it is
0x56.
AD I2C Address
0 0x54
1 0x56
Table 1 I2C Address
4.3. Write or Read
A bit after 7-bit slave Address means to WRITE (0) or to READ (1).
4.3.1. Writing to NTP3000
I2C data can be written on NTP3000 by using modified I2C write operation. Figure 5 (a) shows writing 1-
byte register data procedure. Followed by START condition, master notices the data transfer mode to
NTP3000 by sending slave Address with WRITE operation bit (W). NTP3000 sends acknowledgement
bit (ACK) to master when it receives the slave Address correctly and is ready for response. After
checking the ACK, master sends NTP3000 the sub-Address which means the register Address of
NTP3000. The sub-Address is composed of 7-bit register Address and 1-bit Auto Increment Flag (AIF).
When NTP3000 receives the sub-Address correctly, NTP3000 sends ACK to master. After checking the
ACK, master sends data which means the register value to NTP3000. Master checks ACK and 1-byte
register data writing procedure is finished by initiating the STOP condition.
Notice)
If the sub-Address is floating point coefficient register (0x40 ~ 0x5F), 4-byte register data should be
written.
AIF is used for writing multi-byte to NTP3000. Multi-byte register data writing procedure is shown in
Figure 5 (b), (c).
Copyright © NeoFidelity, Inc. 2005
Preliminary datasheet – NeoFidelity reserves the right to change specifications at any time without prior notice
6
R0.73-11.2006

6 Page



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共有リンク

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部品番号部品説明メーカ
NTP3000

2.1 CHANNEL FULL DIGITAL AMPLIFIER

NeoFidelity
NeoFidelity


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