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PDF TMP93PW40 Data sheet ( Hoja de datos )
| Número de pieza | TMP93PW40 | |
| Descripción | CMOS 16-Bit Microcontroller | |
| Fabricantes | Toshiba Semiconductor | |
| Logotipo |  |
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TMP93PW40
Low Voltage/Low Power
CMOS 16-Bit Microcontrollers
TMP93PW40DF
1. Outline and Device Characteristics
The TMP93PW40 is OTP type MCU which includes 128-Kbyte One-time PROM. Using the
adapter-socket, you can write and verify the data for TMP93PW40.TMP93PW40 has the same
pin-assignment with TMP93CW40 (Mask ROM type) .
Writing the program to built-in PROM, the TMP93PW40 operates as the same way with
TMP93CW40.
000000H
Internal I/O
000080H
001080H
Internal RAM
External area
008000H
Internal ROM
(128 Kbytes)
MCU
TMP93PW40DF
028000H
External area
FFFF00H
FFFFFFH
Reserved
= Internal area
Figure 1.1 Memory Map of TMP93CW40/PW40
ROM
OTP 128 Kbytes
RAM
4 Kbytes
Package
P-LQFP100-1414-0.50F
Adapter Socket
BM11129
030619EBP1
• The information contained herein is subject to change without notice.
• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of TOSHIBA or others.
• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general
can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid
situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to
property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most
recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for
Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..
• The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal
equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are
neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunctionor
failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made
at the customer’s own risk.
• The products described in this document are subject to the foreign exchange and foreign trade laws.
• TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law
and regulations.
• For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality
and Reliability Assurance/Handling Precautions.
93PW40-1
2004-02-10
1 page  
TMP93PW40
Pin Names
P41
CS1
CAS1
P42
CS2
CAS2
P50 to P57
AN0 to AN7
VREFH
VREFL
P60 to P63
PG00 to PG03
P64 to P67
PG10 to PG13
P70
TI0
P71
TO1
P72
TO2
P73
TO3
P80
TI4
INT4
P81
TI5
INT5
P82
TO4
P83
TO5
Table 2.2.2 Names and Functions in MCU Mode (2/4)
Number
of Pins
I/O
Functions
1 I/O Port 41: I/O port (with pull-up resistor).
Output Chip select 1: Outputs 0 if address is within specified address area.
Output Column address strobe 1: Outputs CAS strobe for DRAM if address is within
specified address area.
1 I/O Port 42: I/O port (with pull-down resistor).
Output Chip select 2: Outputs 0 if address is within specified address area.
Output Column address strobe 2: Outputs CAS strobe for DRAM if address is within
specified address area.
8 Input Port 5: Input port.
Input Analog input: Input to AD converter.
1 Input Pin for reference voltage input to AD converter (H).
1 Input Pin for reference voltage input to AD converter (L).
4 I/O Ports 60 to 63: I/O ports that allow selection of I/O on a bit basis
(with pull-up resistor).
Output Pattern generator ports: 00 to 03.
4 I/O Ports 64 to 67: I/O ports that allow selection of I/O on a bit basis
(with pull-up resistor).
Output Pattern generator ports: 10 to 13.
1 I/O Port 70: I/O port (with pull-up resistor).
Input Timer input 0: Timer 0 input.
1 I/O Port 71: I/O port (with pull-up resistor).
Output Timer output 1: Timer 0 or 1 output.
1 I/O Port 72: I/O port (with pull-up resistor).
Output PWM output 2: 8-bit PWM timer 2 output.
1 I/O Port 73: I/O port (with pull-up resistor).
Output PWM output 3: 8-bit PWM timer 3 output.
1 I/O Port 80: I/O port (with pull-up resistor).
Input Timer input 4: Timer 4 count/capture trigger signal input.
Input Interrupt request pin 4: Interrupt request pin with programmable rising/falling
edge.
1 I/O Port 81: I/O port (with pull-up resistor).
Input Timer input 5: Timer 4 count/capture trigger signal input.
Input Interrupt request pin 5: Interrupt request pin with rising edge.
1 I/O Port 82: I/O port (with pull-up resistor).
Output Timer output 4: Timer 4 output pin.
1 I/O Port 83: I/O port (with pull-up resistor).
Output Timer output 5: Timer 4 output pin.
93PW40-5
2004-02-10
5 Page 
TMP93PW40
d. Programming
Program/verify according to the procedures of PROM programmer.
VPP(12.75 V/5 V)
EA
TEST1
TEST2
P33
P17
A16 to
to P10
A0 P27
to
P20
AVCC, VCC
P30
P32
P31
P07
to
P00
RESET
CLK
VCC
OE
CE
PGM
D7
to
D0
X1
X2
VSS
AVSS
P42 to P40,
P37 to P35,
AM8/ AM16
P34
VCC
SECURITY
Figure 3.3.1 PROM Mode Pin Setting
* Use the 10 MHz
resonator in case of
programming and
verification by a general
EPROM programmer.
(2) Programming flow chart
The programming mode is set by applying 12.75 V (programming voltage) to the VPP pin
when the following pins are set as follows,
(VCC: 6.25 V, RESET : “L” level, CLK: “L” level).
While address and data are fixed and CE pin is set to “L” level, 0.1 ms of “L” level pulse is
applied to PGM pin to program the data.
Then the data in the address is verified.
If the programmed data is incorrect, another 0.1 ms pulse is applied to PGM pin.
This programming procedure is repeated until correct data is read from the address. (25
times maximum)
Subsequently, all data are programmed in all addresses.
The verification for all data is done under the condition of VPP = VCC = 5 V after all data
were written.
Figure 3.3.2 shows the programming flow chart.
93PW40-11
2004-02-10
11 Page | ||
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| PDF Descargar | [ Datasheet TMP93PW40.PDF ] | |
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