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P3NA50のメーカーはSTMicroelectronicsです、この部品の機能は「STP3NA50」です。 |
部品番号 | P3NA50 |
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部品説明 | STP3NA50 | ||
メーカ | STMicroelectronics | ||
ロゴ | |||
このページの下部にプレビューとP3NA50ダウンロード(pdfファイル)リンクがあります。 Total 10 pages
STP3NA50
STP3NA50FI
N - CHANNEL ENHANCEMENT MODE
FAST POWER MOS TRANSISTOR
TYPE
STP3NA50
STP3NA50FI
VDSS
500 V
500 V
RDS(on)
<3Ω
<3Ω
ID
3.3 A
2.3 A
s TYPICAL RDS(on) = 2.4 Ω
s ± 30V GATE TO SOURCE VOLTAGE RATING
s 100% AVALANCHE TESTED
s REPETITIVE AVALANCHE DATA AT 100oC
s LOW INTRINSIC CAPACITANCES
s GATE GHARGE MINIMIZED
s REDUCED THRESHOLD VOLTAGE SPREAD
DESCRIPTION
This series of POWER MOSFETS represents the
most advanced high voltage technology. The
optimized cell layout coupled with a new
proprietary edge termination concur to give the
device low RDS(on) and gate charge, unequalled
ruggedness and superior switching performance.
APPLICATIONS
s HIGH CURRENT, HIGH SPEED SWITCHING
s SWITCH MODE POWER SUPPLIES (SMPS)
s DC-AC CONVERTERS FOR WELDING
EQUIPMENT AND UNINTERRUPTIBLE
POWER SUPPLIES AND MOTOR DRIVE
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
VDS Drain-source Voltage (VGS = 0)
VDGR Drain-gate Voltage (RGS = 20 kΩ)
VGS Gate-source Voltage
ID Drain Current (continuous) at Tc = 25 oC
ID Drain Current (continuous) at Tc = 100 oC
IDM(•) Drain Current (pulsed)
Ptot Total Dissipation at Tc = 25 oC
Derating Factor
VISO Insulation Withstand Voltage (DC)
Tstg Storage Temperature
Tj Max. Operating Junction Temperature
(•) Pulse width limited by safe operating area
November 1996
3
2
1
TO-220
3
2
1
ISOWATT220
INTERNAL SCHEMATIC DIAGRAM
Value
STP3NA50
STP3NA50FI
500
500
± 30
3.3 2.3
2.1 1.5
13.2
13.2
80 40
0.64
0.32
2000
-65 to 150
150
Unit
V
V
V
A
A
A
W
W/oC
V
oC
oC
1/10
1 Page STP3NA50/FI
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
Symbol
td(on)
tr
(di/dt)on
Qg
Qgs
Qgd
Parameter
Turn-on Time
Rise Time
Turn-on Current Slope
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Test Conditions
VDD = 250 V ID = 1.5 A
RG = 18 Ω
VGS = 10 V
(see test circuit, figure 3)
VDD = 400 V ID = 3 A
RG = 18 Ω
VGS = 10 V
(see test circuit, figure 5)
VDD = 400 V ID = 3 A VGS = 10 V
Min.
Typ.
14
23
340
21
6
9
Max.
20
30
28
Unit
ns
ns
A/µs
nC
nC
nC
SWITCHING OFF
Symbol
tr(Voff)
tf
tc
Parameter
Off-voltage Rise Time
Fall Time
Cross-over Time
Test Conditions
VDD = 400 V ID = 3 A
RG = 18 Ω VGS = 10 V
(see test circuit, figure 5)
Min.
Typ.
13
11
26
Max.
18
16
35
Unit
ns
ns
ns
SOURCE DRAIN DIODE
Symbol
Parameter
Test Conditions
ISD
ISDM(•)
Source-drain Current
Source-drain Current
(pulsed)
VSD (∗) Forward On Voltage
ISD = 3.3 A VGS = 0
trr Reverse Recovery
Time
Qrr Reverse Recovery
Charge
ISD = 3 A di/dt = 100 A/µs
VDD = 100 V Tj = 150 oC
(see test circuit, figure 5)
IRRM
Reverse Recovery
Current
(∗) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
(•) Pulse width limited by safe operating area
Min.
Typ.
Max.
3.3
13.2
Unit
A
A
1.6
350
4.2
24
V
ns
µC
A
Safe Operating Areas for TO-220
Safe Operating Areas for ISOWATT220
3/10
3Pages STP3NA50/FI
Turn-on Current Slope
Turn-off Drain-source Voltage Slope
Cross-over Time
Switching Safe Operating Area
Accidental Overload Area
Source-drain Diode Forward Characteristics
6/10
6 Page | |||
ページ | 合計 : 10 ページ | ||
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部品番号 | 部品説明 | メーカ |
P3NA50 | STP3NA50 | STMicroelectronics |