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PDF P3NA50 Data sheet ( 特性 )

部品番号 P3NA50
部品説明 STP3NA50
メーカ STMicroelectronics
ロゴ STMicroelectronics ロゴ 

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P3NA50 Datasheet, P3NA50 PDF,ピン配置, 機能
STP3NA50
STP3NA50FI
N - CHANNEL ENHANCEMENT MODE
FAST POWER MOS TRANSISTOR
TYPE
STP3NA50
STP3NA50FI
VDSS
500 V
500 V
RDS(on)
<3
<3
ID
3.3 A
2.3 A
s TYPICAL RDS(on) = 2.4
s ± 30V GATE TO SOURCE VOLTAGE RATING
s 100% AVALANCHE TESTED
s REPETITIVE AVALANCHE DATA AT 100oC
s LOW INTRINSIC CAPACITANCES
s GATE GHARGE MINIMIZED
s REDUCED THRESHOLD VOLTAGE SPREAD
DESCRIPTION
This series of POWER MOSFETS represents the
most advanced high voltage technology. The
optimized cell layout coupled with a new
proprietary edge termination concur to give the
device low RDS(on) and gate charge, unequalled
ruggedness and superior switching performance.
APPLICATIONS
s HIGH CURRENT, HIGH SPEED SWITCHING
s SWITCH MODE POWER SUPPLIES (SMPS)
s DC-AC CONVERTERS FOR WELDING
EQUIPMENT AND UNINTERRUPTIBLE
POWER SUPPLIES AND MOTOR DRIVE
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
VDS Drain-source Voltage (VGS = 0)
VDGR Drain-gate Voltage (RGS = 20 k)
VGS Gate-source Voltage
ID Drain Current (continuous) at Tc = 25 oC
ID Drain Current (continuous) at Tc = 100 oC
IDM() Drain Current (pulsed)
Ptot Total Dissipation at Tc = 25 oC
Derating Factor
VISO Insulation Withstand Voltage (DC)
Tstg Storage Temperature
Tj Max. Operating Junction Temperature
() Pulse width limited by safe operating area
November 1996
3
2
1
TO-220
3
2
1
ISOWATT220
INTERNAL SCHEMATIC DIAGRAM
Value
STP3NA50
STP3NA50FI
500
500
± 30
3.3 2.3
2.1 1.5
13.2
13.2
80 40
0.64
0.32
2000
-65 to 150
150
Unit
V
V
V
A
A
A
W
W/oC
V
oC
oC
1/10

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