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PDF CS5346 Data sheet ( Hoja de datos )
| Número de pieza | CS5346 | |
| Descripción | Stereo Audio ADC | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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CS5346
103-dB, 192-kHz, Stereo Audio ADC with 6:1 Input Mux
ADC Features
Multi-bit Delta–Sigma Modulator
103 dB Dynamic Range
-95 dB THD+N
Stereo 6:1 Input Multiplexer
Programmable Gain Amplifier (PGA)
– ± 12 dB Gain, 0.5-dB Step Size
– Zero-crossing, Click-free Transitions
Stereo Microphone Inputs
– +32 dB Gain Stage
– Low-noise Bias Supply
Up to 192 kHz Sampling Rates
Selectable 24-bit, Left-justified or I²S Serial
Audio Interface Formats
System Features
Power-down Mode
+5 V Analog Power Supply, Nominal
+3.3 V Digital Power Supply, Nominal
Direct Interface with 3.3 V to 5 V Logic Levels
Pin Compatible with CS5345 (*See Section 2
for details.)
General Description
The CS5346 integrates an analog multiplexer, program-
mable gain amplifier, and stereo audio analog-to-digital
converter. The CS5346 performs stereo analog-to-digi-
tal (A/D) conve rsion of 24-bit serial values at sa mple
rates up to 192 kHz.
A 6:1 stereo input multiplexer is included for selecting
between line-level and microphone-level inputs. The
microphone input path includes a +32 dB gain stage
and a low-noise bias voltage supply. The PGA is avail-
able for line or microphone inputs and provides
gain/attenuation of ±12 dB in 0.5 dB steps.
The output of the PGA is followed by an advanced 5th-
order, multi-bit delta-sigma modulator and digital filter-
ing/decimation. Sampled data is transmitted by the
serial audio interface at rates from 8 kHz to 192 kHz in
either Slave or Master Mode.
Integrated level translators allow easy interfacing be-
tween the CS5346 and other devices operating over a
wide range of logic levels.
The CS5346 is available in a 48-pin LQFP package in
Commercial (-40° to +85° C) grade. The CDB5346 Cus-
tomer Demonstration board is also available for device
evaluation and implementation suggestions. Please re-
fer to “Ordering Information” on page 38 for complete
details.
3.3 V to 5 V
I²C/SPI
Control Data
Interrupt
Overflow
Reset
Serial
Audio
Output
3.3 V
Register Configuration
High Pass
Filter
Low-Latency
Anti-Alias Filter
High Pass
Filter
Low-Latency
Anti-Alias Filter
5V
Internal Voltage
Reference
Multibit
Oversampling
ADC
Multibit
Oversampling
ADC
PGA
MUX
PGAA
+32 dB
+32 dB
Left PGA Output
Right PGA Output
Stereo Input 1
Stereo Input 2
Stereo Input 3
Stereo Input 4 /
Mic Input 1 & 2
Stereo Input 5
Stereo Input 6
Preliminary Product Information
This document contains information for a product under development.
Cirrus Logic reserves the right to modify this product without notice.
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2012
(All Rights Reserved)
AUG ‘12
DS861PP3
1 page  
1. PIN DESCRIPTIONS - CS5346
CS5346
48 47 46 45 44 43 42 41 40 39 38 37
SDA/CDOUT
SCL/CCLK
AD0/CS
AD1/CDIN
VLC
RST
AIN3A
AIN3B
AIN2A
AIN2B
AIN1A
AIN1B
1
2
3
4
5
6
7
8
9
10
11
12
CS5346
36 VLS
35 NC
34 NC
33 NC
32 AGND
31 NC
30 NC
29 PGAOUTB
28 PGAOUTA
27 AIN6B
26 AIN6A
25 MICBIAS
13 14 15 16 17 18 19 20 21 22 23 24
Pin Name
SDA/CDOUT
SCL/CCLK
AD0/CS
AD1/CDIN
VLC
RST
AIN3A
AIN3B
AIN2A
AIN2B
# Pin Description
1
Serial Control Data (Input/Output) - SDA is a data I/O in I²C® Mode. CDOUT is the output data line for
the control port interface in SPITM Mode.
2 Serial Control Port Clock (Input) - Serial clock for the serial control port.
3
Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C Mode;
CS is the chip-select signal for SPI format.
4
Address Bit 1 (I²C) / Serial Control Data Input (SPI) (Input) - AD1 is a chip address pin in I²C Mode;
CDIN is the input data line for the control port interface in SPI Mode.
5
Control Port Power (Input) - Determines the required signal level for the control port interface. Refer
to the Recommended Operating Conditions for appropriate voltages.
6 Reset (Input) - The device enters a low-power mode when this pin is driven low.
7 Stereo Analog Input 3 (Input) - The full-scale level is specified in the Analog Characteristics specifica-
8 tion table.
9 Stereo Analog Input 2 (Input) - The full-scale level is specified in the Analog Characteristics specifica-
10 tion table.
DS861PP3
5
5 Page 
DIGITAL FILTER CHARACTERISTICS
CS5346
Parameter (Note 7)
Single-Speed Mode
Passband
(-0.1 dB)
Passband Ripple
Stopband
Stopband Attenuation
Total Group Delay (Fs = Output Sample Rate)
Double-Speed Mode
Passband
(-0.1 dB)
Passband Ripple
Stopband
Stopband Attenuation
Total Group Delay (Fs = Output Sample Rate)
Quad-Speed Mode
Passband
(-0.1 dB)
Passband Ripple
Stopband
Stopband Attenuation
Total Group Delay (Fs = Output Sample Rate)
High-Pass Filter Characteristics
Frequency Response
-3.0 dB
-0.13 dB
Phase Deviation
@ 20 Hz
Passband Ripple
Filter Settling Time
Symbol Min Typ Max Unit
tgd
tgd
tgd
(Note 8)
(Note 8)
0
-
0.5688
70
-
-
-
-
-
12/Fs
0.4896
0.035
-
-
-
Fs
dB
Fs
dB
s
0
-
0.5604
69
-
-
-
-
-
9/Fs
0.4896
0.025
-
-
-
Fs
dB
Fs
dB
s
0
-
0.5000
60
-
-
-
-
-
5/Fs
0.2604
0.025
-
-
-
Fs
dB
Fs
dB
s
-1
20
-
-
- 10
-
-- 0
105/Fs
Hz
Hz
Deg
dB
s
7. Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 17 to 28) are
normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
8. Response shown is for Fs = 48 kHz.
DS861PP3
11
11 Page | ||
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| PDF Descargar | [ Datasheet CS5346.PDF ] | |
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