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PDF 3000 Data sheet ( Hoja de datos )
| Número de pieza | 3000 | |
| Descripción | Memory Controller Hub | |
| Fabricantes | Intel | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de 3000 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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Intel® 3000 and 3010 Chipset
Memory Controller Hub (MCH)
Datasheet
November 2008
Reference Number: 313953 Revision: 002
1 page  
4.3.4
4.3.5
4.3.6
4.3.7
EPLE2D—EP Link Entry 2 Description......................................................... 84
EPLE2A—EP Link Entry 2 Address ............................................................. 85
EPLE3D-EP Link Entry 3 Description .......................................................... 85
EPLE3A—EP Link Entry 3 Address ............................................................. 86
5 Host-PCI Express Bridge Registers (D1:F0) .................................................................... 87
5.1 Configuration Register Details (D1:F0) ................................................................. 90
5.1.1 VID1—Vendor Identification (D1:F0) ......................................................... 90
5.1.2 DID1—Device Identification (D1:F0) ......................................................... 90
5.1.3 PCICMD1—PCI Command (D1:F0) ............................................................ 90
5.1.4 PCISTS1—PCI Status (D1:F0) .................................................................. 92
5.1.5 RID1—Revision Identification (D1:F0) ....................................................... 93
5.1.6 CC1—Class Code (D1:F0) ........................................................................ 93
5.1.7 CL1—Cache Line Size (D1:F0) .................................................................. 93
5.1.8 HDR1—Header Type (D1:F0) ................................................................... 94
5.1.9 PBUSN1—Primary Bus Number (D1:F0)..................................................... 94
5.1.10 SBUSN1—Secondary Bus Number (D1:F0)................................................. 94
5.1.11 SUBUSN1—Subordinate Bus Number (D1:F0) ............................................ 95
5.1.12 IOBASE1—I/O Base Address (D1:F0) ........................................................ 95
5.1.13 IOLIMIT1—I/O Limit Address (D1:F0) ....................................................... 95
5.1.14 SSTS1—Secondary Status (D1:F0) ........................................................... 96
5.1.15 MBASE1—Memory Base Address (D1:F0)................................................... 97
5.1.16 MLIMIT1—Memory Limit Address (D1:F0) .................................................. 97
5.1.17 PMBASE1—Prefetchable Memory Base Address (D1:F0) ............................... 98
5.1.18 PMLIMIT1—Prefetchable Memory Limit Address (D1:F0) .............................. 98
5.1.19 PMBASEU1—Prefetchable Memory Base Address ......................................... 99
5.1.20 PMLIMITU1—Prefetchable Memory Limit Address ........................................ 99
5.1.21 CAPPTR1—Capabilities Pointer (D1:F0) .................................................... 100
5.1.22 INTRLINE1—Interrupt Line (D1:F0)......................................................... 100
5.1.23 INTRPIN1—Interrupt Pin (D1:F0)............................................................ 101
5.1.24 BCTRL1—Bridge Control (D1:F0) ............................................................ 101
5.1.25 PM_CAPID1—Power Management Capabilities (D1:F0)............................... 102
5.1.26 PM_CS1—Power Management Control/Status (D1:F0) ............................... 103
5.1.27 SS_CAPID—Subsystem ID and Vendor ID Capabilities (D1:F0) ................... 104
5.1.28 SS—Subsystem ID and Subsystem Vendor ID (D1:F0) .............................. 104
5.1.29 MSI_CAPID—Message Signaled Interrupts Capability ID (D1:F0)................. 104
5.1.30 MC—Message Control (D1:F0)................................................................ 105
5.1.31 MA—Message Address (D1:F0)............................................................... 106
5.1.32 MD—Message Data (D1:F0) ................................................................... 106
5.1.33 PCI_EXPRESS_CAPL—PCI Express Link Capability List (D1:F0) ................... 106
5.1.34 PCI_EXPRESS_CAP—PCI Express Link Capabilities (D1:F0) ........................ 107
5.1.35 DCAP—Device Capabilities (D1:F0) ......................................................... 107
5.1.36 DCTL—Device Control (D1:F0) ............................................................... 108
5.1.37 DSTS—Device Status (D1:F0) ................................................................ 108
5.1.38 LCAP—Link Capabilities (D1:F0) ............................................................. 109
5.1.39 LCTL—Link Control (D1:F0) ................................................................... 110
5.1.40 LSTS—Link Status (D1:F0) .................................................................... 111
5.1.41 SLOTCAP—Slot Capabilities (D1:F0) ........................................................ 112
5.1.42 SLOTCTL—Slot Control (D1:F0) .............................................................. 113
5.1.43 SLOTSTS—Slot Status (D1:F0) ............................................................... 114
5.1.44 RCTL—Root Control (D1:F0) .................................................................. 114
5.1.45 RSTS—Root Status (D1:F0) ................................................................... 115
5.1.46 PCI_EXPRESS_LC—PCI Express link Legacy Control .................................. 116
5.1.47 VCECH—Virtual Channel Enhanced Capability Header (D1:F0) .................... 116
5.1.48 PVCCAP1—Port VC Capability Register 1 (D1:F0) ...................................... 117
5.1.49 PVCCAP2—Port VC Capability Register 2 (D1:F0) ...................................... 117
5.1.50 PVCCTL—Port VC Control (D1:F0) ........................................................... 118
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
5
5 Page 
Features
Processor Interface
— Supports a single Intel® Pentium® 4,
Intel® Pentium® D, Intel® Celeron® D,
and Dual-Core Intel® Xeon® Processor
3000 Series in the LGA775 package
— Supports Pentium 4 processor FSB
interrupt delivery
— 533/800/1066 MT/s (133/200/266 MHz
core) FSB
— Supports Hyper-Threading Technology
(HT Technology)
— FSB Dynamic Bus Inversion (DBI)
— 36-bit host addressing for access to 8 GB of
memory space
— 12-deep In-Order Queue
— 1-deep Defer Queue
— GTL+ bus driver with integrated GTL
termination resistors
— Supports a Cache Line Size of 64 bytes
DMI Interface
— A chip-to-chip connection interface to
Intel® ICH7
— 2 GB/s point-to-point DMI to ICH7 (1 GB/s
each direction)
— 100 MHz reference clock (shared with PCI
Express Interface)
— 32-bit downstream addressing
— Messages and Error Handling
PCI Express* Interface Support
— Intel® 3000: one PCI Express port (x8/x4/
x1)
— Intel® 3010: two PCI Express ports (two
x8/x4/x1, or one x16)
— Peer-to-peer Writes
— Compatible with the PCI Express Base
Specification Revision 1.0a
— Raw bit rate on data pins of 2.5 Gb/s
resulting in a real bandwidth per pair of
250 MB/s
— Maximum theoretical aggregate bandwidth
of 8 GB/s when x16
System Memory
— 8 GB maximum memory
— Up to two 64-bit wide DDR2 SDRAM
channels
— DDR2 memory DIMM frequencies of
533 MHz and 667 MHz.
— Asymmetric or Interleaved modes
— Bandwidth up to 10.7 GB/s (DDR2 667) in
dual- channel Interleaved mode
— ECC (Error Correcting Code) memory
— 256 Mb, 512 Mb and 1 Gb DDR2
technologies
— Four banks for DDR2 devices up to 512 Mb
density; eight banks for 1 Gb DDR2 devices
— Unbuffered DIMMs only
— Page sizes of 4 KB, 8 KB, and 16 KB
— Opportunistic refresh
— Up to 64 simultaneously open pages
— SPD (Serial Presence Detect) scheme for
DIMM detection support
— Supports configurations defined in the
JEDEC DDR2 DIMM specification only
Package
— 34 mm x 34 mm, 1202 balls, non-grid
pattern
— Lead Free MCH
§
Intel® 3000 and 3010 Chipset Memory Controller Hub (MCH) Datasheet
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet 3000.PDF ] | |
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