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CS495314 の電気的特性と機能

CS495314のメーカーはCirrus Logicです、この部品の機能は「Audio Decoder DSP Family」です。


製品の詳細 ( Datasheet PDF )

部品番号 CS495314
部品説明 Audio Decoder DSP Family
メーカ Cirrus Logic
ロゴ Cirrus Logic ロゴ 




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CS495314 Datasheet, CS495314 PDF,ピン配置, 機能
CS4953xx Data Sheet
FEATURES
Multi-standard 32-bit Audio Decoding plus Post
processing
Supports legacy audio formats and a wide array of post-
processing
— Dolby Digital® EX, Dolby Pro Logic® II, IIx, IIz 7.1,
Dolby Headphone® 2, Dolby Virtual Speaker® 2,
Dolby Volume® (original), Dolby Volume 258(lite),
Audistry®
— DTS-ES 96/24Discrete 7.1, DTS-ESDiscrete 7.1,
DTS-ESMatrix 6.1, DTS Neo:6®, DTS Neural
SurroundDTS Surround Sensation Speaker
— MPEG-2 AACLC 5.1
— SRS® Circle Surround® II, SRS Circle Surround Auto,
SRS Circle Surround Decoder Optimized, SRS
TruVolume7.1 (V 2.1.0.0), SRS TruSurround
HD/HD4®, SRS WOW HD, SRS CS Headphone,
SRS Circle Cinema 3D, SRS Studio Sound HD
— THX® Ultra2, THX Select2
Cirrus Logic’s Applications Library
— Cirrus Original Multi-Channel Surround 2 (COMS2),
Cirrus Band XpandeR, Cirrus Virtualization
Technology (CVT), Cirrus Intelligent Room Calibration
2 (IRC2), Cirrus Bass Enhancement (CBE)
— Crossbar Mixer, Signal Generator
— Advanced Post-Processors including: 7.1 Bass
Manager Quadruple Crossover, Tone Control, 11-
Band Parametric EQ, Delay, 2:1/4:1 Decimator,
1:2/1:4 Upsampler
Up to 12 Channels of 32-bit Serial Audio Input
Audio Decoder DSP Family with
Dual 32-bit DSP Engine Technology
16 Ch x 32-bit PCM Out with Dual 192 kHz S/PDIF Tx
Two SPI/I2CPorts
Customer Software Security Keys
Large On-chip X, Y, and Program RAM & ROM
SDRAM and Serial Flash Memory Support
The CS4953xx DSP family are the enhanced versions of the
CS495xx DSP family with higher overall performance and
lower system cost. The CS4953xx includes all mainstream
audio processing codes in on-chip ROM. This saves external
memory for code storage. In addition, the intensive decoding
tasks of Dolby Digital Surround EX®, AAC multi-channel,
DTS-ES 96/24, THX Ultra2 Cinema and Dolby Headphone
can be accomplished without the expense of external
SDRAM memory.
With larger internal memories than the CS495xx, the
CS49531x is designed to support up to 150 ms per channel
of lip-sync delay. With 150 MHz internal clock speed, the
CS4953xx supports the most demanding post-processing
requirements. It is also designed for easy upgrading.
Customers currently using the CS495xx can upgrade to the
CS4953xx with minor hardware and software changes.
Ordering Information
See page 28 for ordering information.
Serial
Control 1
12 Ch PCM
Audio In
S/PDIF S/PDIF
16 Ch PCM
Audio Out
Serial
Control 2
Parallel
Control
GPIO
Debug
Coyote 32-bit
DSP A
D
M
A
Coyote 32-bit
DSP B
PXY
PXY
Ext. Memory Controller
STC
TMR1
TMR2
PLL
http://www.cirrus.com
Copyright © 2012 Cirrus Logic, Inc.
All Rights Reserved
FEB 2012
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CS495314 pdf, ピン配列
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
9.1 128-Pin LQFP Package Drawing ........................................................................................................... 29
9.2 144-Pin LQFP Package Drawing ........................................................................................................... 30
10 Revision History .....................................................................................................................31
List of Figures
Figure 1. RESET Timing ........................................................................................................................................12
Figure 2. XTI Timing ..............................................................................................................................................12
Figure 3. Serial Control Port - SPI Slave Mode Timing ..........................................................................................15
Figure 4. Serial Control Port - SPI Master Mode Timing ........................................................................................16
Figure 5. Serial Control Port - I2C Slave Mode Timing ..........................................................................................17
Figure 6. Serial Control Port - I2C Master Mode Timing ........................................................................................18
Figure 7. Parallel Control Port - Intel Slave Mode Read Cycle ..............................................................................20
Figure 8. Parallel Control Port - Intel Slave Mode Write Cycle ..............................................................................20
Figure 9. Parallel Control Port - Motorola Slave Mode Read Cycle Timing ...........................................................22
Figure 10. Parallel Control Port - Motorola Slave Mode Write Cycle Timing .........................................................22
Figure 11. Digital Audio Input (DAI) Port Timing Diagram .....................................................................................23
Figure 12. DAI Slave Timing Diagram ...................................................................................................................23
Figure 13. Digital Audio Port Output Timing Master Mode .....................................................................................24
Figure 14. Digital Audio Output Timing, Slave Mode .............................................................................................25
Figure 15. External Memory Interface - SDRAM Burst Read Cycle .......................................................................26
Figure 16. External Memory Interface - SDRAM Burst Write Cycle .......................................................................26
Figure 17. External Memory Interface - SDRAM Auto Refresh Cycle ....................................................................27
Figure 18. External Memory Interface - SDRAM Load Mode Register Cycle ........................................................27
Figure 19. 128-pin LQFP Pin-Out Drawing (CS495303/CS495313) ......................................................................30
Figure 20. 128-pin LQFP Pin-Out Drawing (CS495304/CS495314) ......................................................................31
Figure 21. 144-pin LQFP Pin-Out Drawing (CS495313) ........................................................................................32
Figure 22. 128-pin LQFP Package Drawing .........................................................................................................33
Figure 23. 144-pin LQFP Package Drawing .........................................................................................................34
List of Tables
Table 1. CS4953xx Related Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 2. Device and Firmware Selection Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. CS49530x DSP Memory Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 4. CS49531x DSP Memory Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 6. Environmental, Manufacturing, and Handling Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 7. 128-pin LQFP Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 8. 144-pin LQFP Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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CS495314 電子部品, 半導体
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
Table 2. Device and Firmware Selection Guide1
Device
Pre- Decode Processor
Process
(DSP-A)2
Matrix-processor
(DSP-A)2
Virtualizer-
processor
(DSP-B)2
Post-processor
(DSP-B)2
CS49530x
300 M ACS
CS49531x
(Superset of
CS49530x)
300 M ACS
N/A
Lip Sync
Delay
Stereo PCM
Multi-Channel PCM
(2:1 Down-sampling
Option)
Dolby Digital
AAC
MP3
HDCD
Dolby Pro Logic II/IIx/IIz
7.1
Circle Surround II
(Stereo In)
Cirrus Original Multi-
Channel Surround
(Effects / Reverb
Processor)
Dolby Headphone
Dolby Virtual Speaker
SRS TruSurround XT
THX Select
Down-mix
(Simultaneous Process)
APP
(Advanced Post-
processing)
–Tone Control
–Select 2
–PEQ (up to 11 Bands)
–Delay
–7.1 Bass Manager
–Audio Manager
Same as CS49530x +
DTS
DTS-ES
DTS 96/24
Same as CS49530x +
DTS Neo:6, DTS Neural
Sound
(Stereo In)
Same as CS49530x +
THX Ultra2
1:2 Up-sampling
1.This feature list is a snapshot of features available as of the publication date of this revision of the data sheet. More features may
now be available. Check with your Cirrus Logic Field Application Engineer (FAE) to obtain the latest feature list for the CS49530x
and CS49531x products.
2. Additional processing (MPMA, MPMB, VPM, PPM) post any of the HD audio decoders may be limited. Contact your Cirrus Logic
FAE for concurrency matrix.
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共有リンク

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部品番号部品説明メーカ
CS495313

Audio Decoder DSP Family

Cirrus Logic
Cirrus Logic
CS495314

Audio Decoder DSP Family

Cirrus Logic
Cirrus Logic


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